vhdl

问题 I am trying to implement a Low Pass Filter in an FPGA using VHDL. Now, I worked out all the filter coefficients, but I am having trouble trying to understand how to work with the coefficients, given the fact that they are non-whole numbers. I would appreciate any help with an example of a simple filter implementation in VHDL. Thanks a lot, Chris 回答1: You should convert the coefficients to fix-point numbers. Very short: Chose a precision and multiply all coefficients by the nearest higher

问题 Consider the following type foo is (A, B, C); type foo_vector is array (foo) of std_logic_vector; How do I constrain foo_vector ? It seems like the compiler should be able to constrain the signal if I give it defaults. signal bar : foo_vector : (others => x"0000"); But the compiler just continues to say "Signal cannot be unconstrained" If that's the case then how can I constrain this signal? signal bar : foo_vector(?)(15 downto 0); I am using the Lattice compiler. Alternatively, If I do type

问题 I am writing a code using VHDL to convert 24MHz and 12 MHz clock to 8 MHz clock. Can anyone please help me in this coding? Thanks in advance. 回答1: Is this for an FPGA? Or something else? Are you really dividing a clock, or just a signal? For a divide by three counter, try this link: http://www.asic-world.com/examples/vhdl/divide_by_3.html And for a 2/3: http://www.edaboard.com/thread42620.html 回答2: As Martin has already said, use a clock management device by Xilinx recommendations in order to

问题 I'm confused about a problem I have in VHDL. I make one VGA_display_ characters , so I wanna convert some std_logic_vectors into integer by to_integer unsigned, then I wanna recuperate, in this way I can't use those libraries in the same time. ieee.std_logic_arith.all and ieee.numeric_std.all The error given by quartus: (Error (10621): VHDL Use Clause error at interface.vhd(34): more than one Use Clause imports a declaration of simple name "unsigned" -- none of the declarations are directly

问题 I was trying to return type std_logic_vector by type conversion in vhdl. Here is my code: function mul(num1,num2 : in std_logic_vector(7 DOWNTO 0)) return std_logic_vector is variable v_TEST_VARIABLE1 : integer; variable v_TEST_VARIABLE2 : integer; variable n_times: integer:=1; variable product: integer:=0; begin for n_times in 1 to v_TEST_VARIABLE2 loop product:=product + v_TEST_VARIABLE1; end loop; return std_logic_vector(product); end mul; It gives "Illegal type conversion from std

问题 I'm trying to implement an generic adder tree similar to here. For storing the intermediate results, I need to declare a variable number of signals with variable bitwidth. For example: 4 input values with bitwidth = 8: after first stage: 2 values with bitwidth = 9 after second stage: 1 value with bitwidth = 10 9 input values with bitwidth = 8: after first stage: 5 values with bitwidth = 9 after second stage: 3 values with bitwidth = 10 after third stage: 2 values with bitwidth = 11 after

问题 I want to drive a birectionnal logic signal through the FPGA. PGD_ICD <--> PGD_TARGET for those who have recognized the Microchip ICD3 you know that PGD line is bidirectional. I've read that we can't do something like that but have you any idea ? many thanks 回答1: Passing a bidirectional bus through an FPGA without knowing the bus protocol won't work. While FPGA I/O pins do support tristate logic signals (floating output state), you will need to know when to drive a value onto the output, and

问题 I am getting a warning when i try synthesize,implement, and generate program file from my VHDL Code. When i try to synthesize i get this error WARNING:Xst:647 - Input <BTN_3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. When i Implement it i get this WARNING:PhysDesignRules:367 - The signal <BTN_3_IBUF> is incomplete. The signal does not drive any load pins in

问题 I am getting a warning when i try synthesize,implement, and generate program file from my VHDL Code. When i try to synthesize i get this error WARNING:Xst:647 - Input <BTN_3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. When i Implement it i get this WARNING:PhysDesignRules:367 - The signal <BTN_3_IBUF> is incomplete. The signal does not drive any load pins in

问题 I've received an advice to avoid gated clock because it may cause problems with slacks and timing costraints. But I want to ask what I can consider like a gated clock. For example: This code have gated clock because StopCount gate it. process(ModuleCLK) begin if (rising_edge(ModuleCLK) and StopCount = '0') then if ModuleEN = '0' then RESET <= '0'; POWER <= '1'; EN <= '0'; CLOCK <= '0'; SERIAL <= '0'; elsif This code have also gated clock? process(ModuleCLK) begin if ModuleEN = '0' then RESET