Illegal type conversion VHDL

问题

I was trying to return type std_logic_vector by type conversion in vhdl. Here is my code:

 function mul(num1,num2 : in std_logic_vector(7 DOWNTO 0)) return std_logic_vector is
    variable v_TEST_VARIABLE1 : integer;
    variable v_TEST_VARIABLE2 : integer;
    variable n_times: integer:=1;
    variable product: integer:=0;
    begin 
      for n_times in 1 to v_TEST_VARIABLE2 loop
        product:=product + v_TEST_VARIABLE1;
      end loop;
    return std_logic_vector(product);
  end mul;

It gives "Illegal type conversion from std.standard.integer to ieee.std_logic_1164.std_logic_vector (numeric to array)." on compilation. How do I return std_logic_vector in such a code?

回答1:

You must first convert it to an unsigned. I hope you're using numeric_std? If so, your code looks like this. Note that to use to_unsigned you must know the length of your output std_logic_vector. So this either needs to be an input to your function or you can bound the return vector:

return std_logic_vector(to_unsigned(product, length));

More information about how to convert std_logic_vector to integer.

回答2:

See Russell's post first. If you use the VHDL-2008, numeric_std_unsigned package, then you can use just one conversion:

use ieee.numeric_std_unsigned.all ; 
...
return to_std_logic_vector(product, length) ;  -- long form

-- alternate short form
return to_slv(product, length) ;

Usage warning: for synthesis, I consider VHDL-2008 items to be on the bleeding edge of support. Hence, while I use VHDL-2008 frequently in my testbenches, I try to limit the usage of it in my RTL code to what can't be done using other methods. However, if you ever want to use code like this, it is it is important to try it out in your synthesis tool and submit a bug report against it if it does not work - that is the only way change happens.

来源：https://stackoverflow.com/questions/24308180/illegal-type-conversion-vhdl

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type-conversion

vhdl