vhdl

Decimal number on 7 segment display

由 回眸只為那壹抹淺笑 提交于 2020-01-23 03:05:09
问题 I've got a big problem with VHDL for a project. I want to see on 7 segment display a number that user sets with switches. For example if the low-order 5 switches are turned on then they will represent the binary number "11111" that is 31 in decimal. So I want to see 31 on 7 segment display. To do that I plan these steps: Insert the 5 value of the switch into an array Convert the array into an integer number See the integer number into 7 segment display Point 1) insert into an array signal

Multiplication by power series summation with negative terms

由 一笑奈何 提交于 2020-01-22 15:32:05
问题 How can I calculate a floating point multiplicand in Verilog? So far, I usually use shift << 1024 , then floating point number become to integer. Then I do some operations, then >> 1024 to obtain a fraction again. For example 0.3545 = 2^-2 + 2^-4 + ... I have question about another way, like this. I don't know where does the minus (-) comes from: 0.46194 = 2^-1 - 2^-5 - 2^-7 + 2^-10. I have just look this from someone. but as you way, that is represented like this 0.46194 = 2^-2 + 2^-3 + 2^-4

移位寄存器的设计（VHDL）及testbench的编写

由 ＊爱你＆永不变心＊ 提交于 2020-01-22 02:33:04
移位寄存器是一种常用的存储元件，此处由D触发器构成，如下图所示。 当时钟边沿到来时，存储在移位寄存器的数据朝一个方向移动一个BIT位。 移位寄存器的功能主要为：串并转换，并串转换和同步延迟。 vhdl代码如下： 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity shiftreg_rb is --实体说明及端口说明 5 port( 6 si,clr_bar,clk:in std_logic; 7 qout:buffer std_logic_vector(3 downto 0)--由于qout端口既是当前D触发器的输入也是上一个D触发器的输出。 8 ); --即qout信号是被驱动源驱动的同时还要驱动下一个端口。 9 end entity shiftreg_rb; --此情况下要使用buffer模式的端口。 10 11 architecture behavior of shiftreg_rb is 12 begin 13 process (clk) ---当时钟发生变化（上升沿或下降沿发生），执行进程 14 begin 15 if clk='1' then --时钟上升沿触发 16 if clr_bar = '0' then --时钟使能 17 qout <= "0000"; 18 else 19 qout(0) <

vhdl code (for loop)

由 [亡魂溺海] 提交于 2020-01-21 09:46:45
问题 Description: I want to write vhdl code that finds the largest integer in the array A which is an array of 20 integers. Question: what should my algorithm look like, to input where the sequential statements are? my vhdl code: highnum: for i in 0 to 19 loop i = 0; i < 20; i<= i + 1; end loop highnum; This does not need to be synthesizable but I dont know how to form this for loop a detailed example explaining how to would be appreciated. 回答1: First of all you should know how have you defined

Passing Generics to Record Port Types

由 南楼画角 提交于 2020-01-20 04:05:48
问题 I did recently start to use records for my port definitions, especially if I want to group signals that belong to a certain interface. However, the problem I'm facing here is that I cannot pass, say the width of a std_logic_vector, to the entity by means of a generic. So what I basically want to do is the following: library ieee; use ieee.std_logic_1164.all; use work.math_pkg.all; package fifo_pkg is type fifo_in_type is record data_in : std_logic_vector(DATA_WIDTH_??- 1 downto 0); rd : std

Generic Records (attempted via vhdl 2008 generic package)

由 二次信任 提交于 2020-01-19 13:15:29
问题 I want to write a library for component C , the component is split internally into two supcomponents c1 and c2 , which are configurable by generics. The submodules should be connected by a record, that depends on the generics. The record should also be used within the components. Usually I would instantiate the record in a package , and use the package in the files for the subcomponents and in the file for the component. Since it is generic I figured using a generic Package (VHDL-2008) might

Generic Records (attempted via vhdl 2008 generic package)

由 为君一笑 提交于 2020-01-19 13:10:35
问题 I want to write a library for component C , the component is split internally into two supcomponents c1 and c2 , which are configurable by generics. The submodules should be connected by a record, that depends on the generics. The record should also be used within the components. Usually I would instantiate the record in a package , and use the package in the files for the subcomponents and in the file for the component. Since it is generic I figured using a generic Package (VHDL-2008) might

Modelsim / reading a signal value

由 你说的曾经没有我的故事 提交于 2020-01-17 08:03:33
问题 In my simulation, I want to have RW access to signals whereever there are in the project. To get the write access, I use the "signal_force" procedure from the modelsim_lib library. But to get the read access I havn't find the corresponding function. The reason why signal_force fit my needs is that I'm working with input text files, so I have the name and the value of the signal from a "string" or a "line" variable and I can directly give these variable to the fonction. I cannot use the "init

How to write a record to memory and get it back in VHDL?

由 感情迁移 提交于 2020-01-17 07:21:48
问题 In VHDL pseudo-code what I would like to achieve is: type tTest is record A : std_logic_vector(3 downto 0); B : std_logic_vector(7 downto 0); C : std_logic_vector(0 downto 0); end record tTest; . . . signal sTestIn : tTest; signal sMemWrData : std_logic_vector(fRecordLen(tTest)-1 downto 0); signal sMemRdData : std_logic_vector(fRecordLen(tTest)-1 downto 0); signal sTestOut : tTest; . . . sMemWrData <= fRecordToVector(sTestIn); -- At some point sMemRdData gets the data in sMemWrData...

How to write a record to memory and get it back in VHDL?

由 人盡茶涼 提交于 2020-01-17 07:21:16
问题 In VHDL pseudo-code what I would like to achieve is: type tTest is record A : std_logic_vector(3 downto 0); B : std_logic_vector(7 downto 0); C : std_logic_vector(0 downto 0); end record tTest; . . . signal sTestIn : tTest; signal sMemWrData : std_logic_vector(fRecordLen(tTest)-1 downto 0); signal sMemRdData : std_logic_vector(fRecordLen(tTest)-1 downto 0); signal sTestOut : tTest; . . . sMemWrData <= fRecordToVector(sTestIn); -- At some point sMemRdData gets the data in sMemWrData...
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