VHDL _ TO_INTEGER

问题

I'm confused about a problem I have in VHDL.

I make one VGA_display_ characters, so I wanna convert some std_logic_vectors into integer by to_integer unsigned, then I wanna recuperate, in this way I can't use those libraries in the same time.

ieee.std_logic_arith.all and ieee.numeric_std.all The error given by quartus:

(Error (10621): VHDL Use Clause error at interface.vhd(34): more than one Use Clause imports a declaration of simple name "unsigned" -- none of the declarations are directly visible Error (10784): HDL error at syn_arit.vhd(26): see declaration for object "unsigned" bellow my code :

to_integer

conv_std_logic_vector

回答1:

My advice is: don't use ieee.std_logic_arith. It's proprietary (not officially part of VHDL) and causes far, far more problems than it solves.

Use only numeric_std and you can do everything you need:

to_integer(unsigned(X)) and to_integer(signed(X)), where X is an std_logic_vector.

To convert back in the other direction:

std_logic_vector(to_unsigned(K, N)) and std_logic_vector(to_signed(K, N)) where K is the integer to convert and N is the number of bits.

来源：https://stackoverflow.com/questions/59058126/vhdl-to-integer