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VHDL No Function declaration for operator “-”

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问题 So i have a task to do the mod operation between 2 vectors(called here dividendo and divisor), so what i need is dividendo mod divisor. We have some restrictions on this code, that is, we cant use iee_std_logic_1164, textio, etc. I think the only libraries allowed are IEEE and IEEE.numeric_bit The algorithm to this operation tells me to: while(dividendo >= divisor){ dividendo = dividendo - divisor } return dividendo And then i wrote this vhdl file: library IEEE; entity resto is port (clock ,

arctan function with cordic with vhdl

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问题 I want to design arctan function with VHDL for using in demodulator design. I need a division & arctan function block. I have two signals, assumed that sin(alpha) and cos(alpha) from previos blocks. I want to retrieve alpha with using division [sin(alpha)/cos(alpha) = tan(alpha)] and then arctan function. I found that it is possible to do that with cordic algortihm, but a bit confused. Do you have any recommendation, docs or sth. how to design division & arctan with cordic in vhdl? Thanks in

arctan function with cordic with vhdl

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arctan function with cordic with vhdl

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VHDL: Button debouncing (or not, as the case may be)

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问题 I've read through the other posts but can't seem to fix mine. I'm new to VHDL so I'm sure it's a simple fix. In short, the button isn't debouncing. The code compiles and the bitstream programs. In the testbench, button presses work, but the output LEDs don't change. On the board, pressing a button makes random LEDs light up (I presume because of bouncing). According to the schematic the inputs are going through the debouncers. Can anyone identify the issue? And any other hints and tips are

VHDL indexed name issue

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问题 i get this error in this code: ter.vhd(31): Cannot resolve indexed name (type ieee.std_logic_1164.STD_ULOGIC) as type std.STANDARD.BOOLEAN. any idea how to fix it? i sincerly don't get what's wrong, tried with a web search, but nothing. thanks in advance! LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY inverter IS GENERIC(size: integer); PORT ( a : IN std_ulogic_vector(size-1 DOWNTO 0); b : OUT std_ulogic_vector(size-1 DOWNTO 0); carry : OUT std_ulogic; mode : IN std_ulogic ); END ENTITY

VHDL truncation leads to malfunction of an implemented FIR Filter

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问题 I implemented a standard form FIR Filter in VHDL. My goal was to create a low pass with a cutoff frequency at 5kHz. The ADC hands me a new sample about every 20us, so with a frequency of about 50kHz. My analog input signal is a 200Hz sine wave with an additional 5500Hz sine wave. What I expect from the FIR filter is to filter out the high frequency. The FIR should work without any software, just digital Hardware. From the ADC, I receive a 12 Bit Input. The DAC also works with 12 Bit to

How to declare output array in VHDL?

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问题 In VHDL how we can declare output array. I know to how to declare a signal as array, by first declaring the type and then defining a signal as this type. Is it possible to do same on output? 回答1: If you want to declare a new type of an array for use on module output, thus not use some existing array type like std_logic_vector , then the type must be declared in a package, in order to make the type available where the module is instantiated. Example below: library ieee; use ieee.std_logic_1164

[高级篇] 在qucs中使用verilog

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为了确保能够正确运行，请确保你现在程序版本为 Qucs 0.0.18 其实将verilog程序放入qucs并不是一件复杂的事情，qucs已经足够简化我们的工作，我们只需要将模块的源代码复制到当前qucs的工作目录下qucs就能进行一系列智能的操作，包括自动添加到工程，以及能够自动识别我们verilog的模块的端口列表。打开qucs，现在Verilog标签下没有任何文件，我们只需要将我们的verilog的.v文件拷贝过来qucs就能自动识别了。一个verilog的半加器代码，这里verilog标签下已经识别到我们的文件了，如果qucs没有刷新在Projects下重新点击一下工程的名字就能看到文件添加过来了。然后鼠标点击一下这个main.v，之后鼠标移到我们的原理图上就会出现一个子电路，四个端口，和我们程序里的两个输入两个输出一致。 qucs非常漂亮！然后我们进行一个数字的仿真. 注意，在digital simulation中我们需要将model的值修改为verilog,因为还有一个选项是VHDL,所以理论上VHDL的代码也能仿真。点击OK之后我们就算做好工作了，然后仿真一下，用真值表显示一下我们的半加器是否正确。 qucs 0.0.18的仿真比老版本的快速多了，而且以前版本偶尔会出现仿真卡住的现象也消失了，新版本做的修改还是挺大的。这个仿真可以将模块用于电路中

VHDL - ror and rol operations

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问题 How can I solve this problem? reg variable is defined as: signal reg:STD_LOGIC_VECTOR(7 downto 0):="00000001"; There is a problem with ror operation in the code below. The error message is: Line 109: Syntax error near "ror". Line 108: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "=" -- process(clk1,up_down,enable,reset) begin if up_down="1" then reg ror 1; end if; end process; 回答1: Your problem is the the ror operator is not defined for std