tie two inout together vhdl

问题

I want to drive a birectionnal logic signal through the FPGA. PGD_ICD <--> PGD_TARGET for those who have recognized the Microchip ICD3 you know that PGD line is bidirectional. I've read that we can't do something like that but have you any idea ? many thanks

回答1:

Passing a bidirectional bus through an FPGA without knowing the bus protocol won't work.

While FPGA I/O pins do support tristate logic signals (floating output state), you will need to know when to drive a value onto the output, and when to tristate the output (high impedence, or 'Z').

Once you have a signal (for example out_enable) that is '1' when you want to drive a value and '0' when the output should be floating, you can use a tri-state buffer to drive the output:

out_pin <= out_signal when(out_enable='1') else 'Z';

来源：https://stackoverflow.com/questions/17297690/tie-two-inout-together-vhdl