VHDL Gated Clock how to avoid

问题

I've received an advice to avoid gated clock because it may cause problems with slacks and timing costraints. But I want to ask what I can consider like a gated clock. For example:

This code have gated clock because StopCount gate it.

process(ModuleCLK)
begin
    if (rising_edge(ModuleCLK) and StopCount = '0') then
       if ModuleEN = '0' then
           RESET <= '0';
           POWER <= '1';
           EN <= '0';
           CLOCK <= '0';
           SERIAL <= '0';
       elsif

This code have also gated clock?

    process(ModuleCLK)
    begin
        if ModuleEN = '0' then
               RESET <= '0';
               POWER <= '1';
               EN <= '0';
               CLOCK <= '0';
               SERIAL <= '0';
        elsif (rising_edge(ModuleCLK)) then

回答1:

The term "gated clock" is often used in ASIC technology for a clock where the clock pulse is only generated when a condition is true (1), so the gated clock is a property of the clock source. A gated clock can be made with a latch and AND gate, like show below, and that kind of design requires special attention to address the timing issues you mention, thus is not suited for FPGA design:

The code you have shown uses an enable on the flip-flop to update the flip-flop value depending on the enable, so this is a clock enable, not a gated clock.

The first code can, and should, be written as:

process (ModuleCLK) is
begin
    if rising_edge(ModuleCLK) then
        if StopCount = '0' then
            ...  -- Update at clock if StopCount = '0'

This reflect how the design is typically implemented in a FPGA, where the flip-flop is always clocked (ModuleCLK) but where the output is only updated if the condition (StopCount = '0') is true.

The second code example looks like asynchronous reset, except that the code should have reset condition (ModuleEN) in the sensitivity list (missing in the question code). The asynchronous reset occurs since no clock clock is required for the flip-flops to change value; the only requirement is that the reset condition is true, and then a change of value occurs asynchronously to any clock.

So a way to properly write flip-flops in VHDL, with input a and output z, is like:

process (reset, clock) is
begin
  if reset = '1' then
    z <= '0';
  elsif rising_edge(clock) then
    if enable = '1' then
      z <= a;
    end if;
  end if;
end process;

In Altera Quartus II this creates RTL figure like:

The implementation in an Arria II device is then:

This shows that the flip-flop up actually updated at every rising edge of the clock, so the clock enable is implemented through a combinatorial design (LUT), where the current data is feed back to the flip-flop when enable is false (0), or new data is given from a when enable is true (1).

来源：https://stackoverflow.com/questions/29674828/vhdl-gated-clock-how-to-avoid

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vhdl

clock

fpga