VHDL; How do I constrain a unconstrained std_logic_vector within a constrained array

问题

Consider the following

type foo is (A, B, C);
type foo_vector is array (foo) of std_logic_vector;

How do I constrain foo_vector? It seems like the compiler should be able to constrain the signal if I give it defaults.

signal bar : foo_vector : (others => x"0000");

But the compiler just continues to say "Signal cannot be unconstrained"

If that's the case then how can I constrain this signal?

signal bar : foo_vector(?)(15 downto 0);

I am using the Lattice compiler.

Alternatively, If I do

type baz_vector is array (natural range <>) is std_logic_vector;

And I try to constrain the signal by doing this:

signal baz_vector_signal : baz_vector(1 downto 0)(15 downto 0);

The code compiles. So I know that the compiler is capable of handling unconstrained arrays (VHDL2008).

回答1:

Your code snippets don't provide a minimal, reproducible example.

You're attempting to provide an element constraint for the element of type std_logic_vector while the array index is already constrained.

That's possible:

library ieee;
use ieee.std_logic_1164.all;

package cjc_pkg is
    type foo is (A, B, C);
    type foo_vector is array (foo) of std_logic_vector;
    signal bar: foo_Vector (open) (3 downto 0) := (others => (others => '0'));
end package;

using an array constraint found in IEEE Std 1076-2008 5.3.2 Array types, 5.3.2.1 General, (the BNF) in the subtype indication for the declaration of signal bar:

constrained_array_definition ::=
array index_constraint of element_subtype_indication

subtype_indication is defined 6.3 Subtype declarations and consist of a optional resolution indication, type mark and constraint. Here we are dealing with the unconstrained element.

From 6.3:

constraint ::=
      range_constraint
    | array_constraint
    | record_constraint

element_constraint ::=
      array_constraint
    | record_constraint

which bounces us back to 5.3.2.1:

array_constraint ::=
index_constraint [ array_element_constraint ]
| ( open ) [ array_element_constraint ]

array_element_constraint ::= element_constraint
...
index_constraint ::= ( discrete_range { , discrete_range } )

discrete_range ::= discrete_subtype_indication | range

An array constraint may be used to constrain an array type or subtype (see 5.3.2.2 and 6.3).

An array object is characterized by the number of indices (the dimensionality of the array); the type, position, and range of each index; and the type and possible constraints of the elements. The order of the indices is significant.

You can use (open) as a space holder to skip over a constrained index preserving the order significance of the constrained index.

The example will analyze with a -2008 compatible VHDL implementation.

来源：https://stackoverflow.com/questions/59002897/vhdl-how-do-i-constrain-a-unconstrained-std-logic-vector-within-a-constrained-a

标签

vhdl