vhdl

问题 can anyone tell me about the difference between below written statement. signal A: **unsigned**(3 downto 0); signal B: **std_logic_vector**(3 downto 0); 回答1: Both std_logic_vector and unsigned are unconstrained arrays of std_logic . As is the signed type. std_logic_vector is declared in the std_logic_1164 package; unsigned and signed are declared in the package numeric_std . All three types are identical; the only difference is their names. So, what's the point of that? The point is well

问题 At first I wanna point out that this is my first attempt with VHDL so be kind. I want to read the X1 ... X4 inputs and produce the sum of the ones at the output. This my code library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity counter_of_aces is Generic(N: integer := 3); port( X1, X2, X3, X4 : IN BIT; count: out std_logic_vector(N-1 downto 0)); end counter_of_aces; architecture behavioral of counter_of_aces is signal counter : std_logic_vector(Ν-1 downto 0); begin process (X1, X2, X3, X4) begin

问题 How do you concatenate bits in VHDL? I'm trying to use the following code: Case b0 & b1 & b2 & b3 is ... and it throws an error Thanks 回答1: The concatenation operator '&' is allowed on the right side of the signal assignment operator '<=', only 回答2: Here is an example of concatenation operator: architecture EXAMPLE of CONCATENATION is signal Z_BUS : bit_vector (3 downto 0); signal A_BIT, B_BIT, C_BIT, D_BIT : bit; begin Z_BUS <= A_BIT & B_BIT & C_BIT & D_BIT; end EXAMPLE; 回答3: You are not

问题 How do you concatenate bits in VHDL? I'm trying to use the following code: Case b0 & b1 & b2 & b3 is ... and it throws an error Thanks 回答1: The concatenation operator '&' is allowed on the right side of the signal assignment operator '<=', only 回答2: Here is an example of concatenation operator: architecture EXAMPLE of CONCATENATION is signal Z_BUS : bit_vector (3 downto 0); signal A_BIT, B_BIT, C_BIT, D_BIT : bit; begin Z_BUS <= A_BIT & B_BIT & C_BIT & D_BIT; end EXAMPLE; 回答3: You are not

问题 So, I have to create a generic N-bit adder with carry in and carry out. I have made two fully working architectures so far, one using the generate function and one using the rtl description as follows: entity: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder_n is generic (N: integer:=8); port ( a,b: in std_logic_vector(0 to N-1); cin: in std_logic; s: out std_logic_vector(0 to N-1); cout: out std_logic); end adder_n; architectures 1 and 2: --STRUCT

问题 I try to design a bch code as a shift register, so I have this schematic: (clickable) And I made a VHDL code in Altera Quartus to design this shift register with loops, the compilation works but it doesn't make the expected result during the simulation in ModelSim (no output). It may have some errors in my code: -- Library declaration LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.std_logic_unsigned.ALL; -- Entity declaration ENTITY bchcode_implementation

问题 I am new to VHDL and trying to make a delay/gate application for programmable FPGA, with adjustable lenght of delay and gate output. As soon as the input signal is recieved, the thing should ignore any other inputs, until generating of gate signal is finished. I want to use this component for 8 different inputs and 8 different outputs later, and set desired delay/gate prameters separately for each one by means of writing registers. When trying to compile in Quartus II v 11.0 i am getting this

问题 I am new to VHDL and trying to make a delay/gate application for programmable FPGA, with adjustable lenght of delay and gate output. As soon as the input signal is recieved, the thing should ignore any other inputs, until generating of gate signal is finished. I want to use this component for 8 different inputs and 8 different outputs later, and set desired delay/gate prameters separately for each one by means of writing registers. When trying to compile in Quartus II v 11.0 i am getting this

问题 I'm trying to configure a lattice MachX03's internal Oscillator. I read the MachXO3 sysCLOCK PLL Design and Usage Guide* and tried using the vhdl code found on page 31 of the documente, but I keep getting this error (VHDL-1261) syntax error near COMPONENT. Can someone tell me how I can get the clock to work using VHDL? here is the code I'm trying to use: LIBRARY lattice; library machXO3; use machXO3.all; COMPONENT OSCH GENERIC( NOM_FREQ: string := "53.20"); --53.20MHz, or can select other

问题 I'm trying to configure a lattice MachX03's internal Oscillator. I read the MachXO3 sysCLOCK PLL Design and Usage Guide* and tried using the vhdl code found on page 31 of the documente, but I keep getting this error (VHDL-1261) syntax error near COMPONENT. Can someone tell me how I can get the clock to work using VHDL? here is the code I'm trying to use: LIBRARY lattice; library machXO3; use machXO3.all; COMPONENT OSCH GENERIC( NOM_FREQ: string := "53.20"); --53.20MHz, or can select other