found '0' definitions of operator “+” in VHDL

问题

At first I wanna point out that this is my first attempt with VHDL so be kind. I want to read the X1 ... X4 inputs and produce the sum of the ones at the output. This my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity counter_of_aces is 
  Generic(N: integer := 3);
     port( X1, X2, X3, X4 : IN BIT; 
        count: out std_logic_vector(N-1 downto 0)); 
end counter_of_aces;

architecture behavioral of counter_of_aces is 
signal counter : std_logic_vector(Ν-1 downto 0);
begin 
  process (X1, X2, X3, X4) 
  begin
    counter <= "0";
    if(X1='1' OR X2='1' OR X3='1' OR X4='1')then 
        counter <= counter + "1"; --O counter λειτουργεί ως στοιχείο μνήμης 
    else
        counter <= counter;
    end if; 
  end process; 
end behavioral;

and I get the following errors

ERROR:HDLCompiler:69 - Line 11: <í> is not declared.
ERROR:HDLCompiler:1731 - Line 17: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:HDLCompiler:854 - Line 10: Unit <behavioral> ignored due to previous errors.

Which "i" is it referring to and what about the others? Thanks in advance.

回答1:

Start your VHDL with

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

回答2:

These are observations based analyzing the example code a simulator.

ERROR:HDLCompiler:69 - Line 11: <í> is not declared.

This is caused by a non ISO 8859-1 character. I replaced the N with a new N and got past that point. My analyzer pointed at line 11, character 36 and examination showed a two byte character there (X"CE9D").

A VHDL analyzer constructs lexical elements out of specific subsets of the ISO 8859-1 character. Comments can contain any characters in VHDL -2008, while previous revisions of the standard required comments to be comprised of the graphic character subset.

ERROR:HDLCompiler:1731 - Line 17: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

The context of overload resolution for operator overload functions depends on signatures - the types and number of parameters and type of the return value. A VHDL analyzer will only look where it's directed to other than for an implicit context clause available to every design unit:

   library STD, WORK; use STD.STANDARD.all;

This is why we add the likes of:

    library ieee;
    use ieee.std_logic_1164.all;

to make all the declarations in library ieee package std_logic_1164 visible so they can be used in a design specification.

Without adding the right use and library clauses the analyzer can't find a "+" function with a signature of [std_logic_vector string return std_logic_vector].

to provide the overload function for the "+" operator on line 17:

        counter <= counter + "1"; --O counter λειτουργεί ως στοιχείο μνήμης 

The string literal "1" would have it's type determined from context (here the entire assignment.

There are two candidate packages for providing an operator overload function: std_logic_unsigned from Synopsys and numeric_std_unsigned a -2008 IEEE package. Neither are made visible currently by a use clause.

Because non- ISO 8859-1 characters are found in the comment it seems you have a IEEE Std 1076-2008 compliant analyzer.

For older VHDL implementations you can stick with the Synopsys package, write your own "+" function, or use type conversions with package numeric_std:

    counter <= std_logic_vector(unsigned(counter) + "1");

There's are additional issues

1. An enable for a latch shouldn't be combinatorial derived. There can be different routing delays or timing causing glitches.

2. counter(N - 1 downto 0) depends on synthesis (mapping) for implementation behavior to match simulation. If implemented as a latch with an increment there's a feedback path (counter <= counter + "1";) that will produce gated oscillation on the counter outputs. An increment is guaranteed to invert at least one input. Output frequencies would be dependent on routing delays, latch and increment delays.

3. There are historical synthesis attributes used to direct the else assignment of counter to itself be implemented in logic. Otherwise a synthesis tool would ignore them (as do simulators mostly, an assignment without a change in effective value doesn't cause an event). The attributes likely have been useful for Earle latches in CPLDs while FPGA vendors typically manage all aspects of implementing latches.

回答3:

try this,

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

来源：https://stackoverflow.com/questions/26598471/found-0-definitions-of-operator-in-vhdl