vhdl

问题 I have this VHDL code, it should work as a sine generator with lookup table. I keep getting error "Missing EOF at function", or just "syntax error" in modelsim. I have the syntax from some online tutorial, and it seems to be correct. What is wrong? function WAVE(X : integer) -- here is the error marker return integer is variable foo: integer; begin WITH X SELECT foo := 0 WHEN 0, 4 WHEN 1, 7 WHEN 2, 11 WHEN 3, 14 WHEN 4, 18 WHEN 5, 21 WHEN 6, 25 WHEN 7, 28 WHEN 8, 32 WHEN 9, 35 WHEN 10, 38

问题 I was wondering is there was a way to defined a type with a size parameter in VHDL. e.g. type count_vector(size: Natural) is unsigned (size-1 downto 0); and then later on do something like variable int : count_vector(32) := (others => '0'); variable nibble : count_vector(4) := (others => '0'); Essentially, is there a way to defined an "array-like" type, or is that not allowed by syntax? I am currently trying to use generics for re-usability, but I would like to be able to take maximal

问题 I am looking at this example and below answer which is a nice solution to produce two's complement: library ieee; use ieee.numeric_std.all; entity twoscomplement is generic ( Nbits : positive := 8 ); port ( A : in unsigned (Nbits-1 downto 0); Y : out signed (Nbits downto 0) ); end entity twoscomplement; architecture a1 of twoscomplement is begin Y <= -signed(resize(A, Y'length)); end architecture; I want to use the said example to have two's complement and then make a " 16-bit subtractor ".

问题 I'm pretty new to VHDL (and digital circuits in general), and I'm trying to implement a counter of two digits using BCD style blocks. External to this circuit there is going to be buttons, which when pressed, will bump the digit of interest up by one (much like an alarm clock would). This is an asynchronous action, and will occur when in some form of edit mode (externally enforced). The code I have written works fine without the "elsif rising_edge(digitUp1) then" and "elsif rising_edge

问题 I have the following source code from the CD attached with "Fundamental of Digital Design" book. When I tried run the program, it gave me the following error: Compiling Fig17_13.vhd... C:\Users\SPIDER\Desktop\EE460\The Final Project\Fig17_13.vhd(25): Warning C0007 : Architecture has unbound instances (ex. ct2) Done How can I fix this issue? Here is the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity c74163test is port(ClrN

问题 The code that is causing problems looks like a normal xnor operation as you can see below: S(1) <= L(16) xnor L(26); This line causes the following error: ncvhdl_p: *E,EXPSMI (HDL/aes_sbox_enc_depth16.vhd,169|14): expecting a semicolon (';') [9.5.1]. ncvhdl_p: *F,MAXERR: maximum error count reached (1). TOOL: ncvhdl 10.20-s075: Exiting on Feb 14, 2012 at 12:56:05 GMT (total: 00:00:01) Anyone an idea what is going wrong here, the semicolon is clearly there. Is it possible that VHDL does not

问题 I have a VHDL package that defines a function (forward declaration) and a constant. The constant's value is calculated by that function, whose body is located in the package body. As of now ModelSim/QuestaSim is the only tool that does not like this code. It needs 2 packages so the body was parsed before the constant declaration. package test is function mytest(param : boolean ) return boolean; constant value : boolean := mytest(TRUE); end package; package body test is function mytest(param :

问题 I want to create an address Decoder that is flexible enough for me to use when changing the number of bits of the selector and of the decoded output signals. So, instead of having a static (fixed input/output size) Decoder that looks something like this : entity Address_Decoder is Generic ( C_INPUT_SIZE: integer := 2 ); Port ( input : in STD_LOGIC_VECTOR (C_INPUT_SIZE-1 downto 0); output : out STD_LOGIC_VECTOR ((2**C_INPUT_SIZE)-1 downto 0); clk : in STD_LOGIC; rst : in STD_LOGIC ); end

问题 I have a VHDL entity with a generic parameter list. The architecture to this entity calculates several constants, which are needed to create the intended functionality. Is it possible to access one of these constants from outside? Example 1: Let's say there is a FIFO that decides based on DEPTH and OUTREG what the best implementation is (register based, SRL based or BlockRAM based). Depending on this the minimum delay through the FIFO can vary from 1 to 2 cycles. Example 2: Consider the same

问题 I'm learning to code on Xilinx (VHDL). Next, I want to make a simple microprocessor/microcontroller and on the way learn a little about slice components. So my goal is try to code an 8 bits microprocessor using an AMD 2901 (4 bits-slice). (I already have the code of the 2901 and all its information about its input and output signals.) I know the first step would be make the architecture of the microprocessor so I ended up with something like this (I understand that the bandwidth of the bus