vhdl | 易学教程

VHDL keypad code issues

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问题 I have a 4x3 keypad, i wrote this FSM for interfacing it with my Nexys2 board, trouble I am having here is When I run the code, the LEDs glow without any key pressed, it shows random combinations automatically When I press a key it shows that particular combination then goes on to the next condition of ROW without any key pressed. And sometimes it does not even respond if i press a key. What is happening? What is wrong with this code? I am clueless. Can someone point out the mistakes and

xilinx软件ISE14.2+modelsim10.1a联合仿真自定义IP核过程

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这个五一也算轻松过了，偶尔打开软件瞅瞅，或者干脆就完游戏去了，反正放假嘛。。也是零零散散的弄了下modelsim+ISE联合仿真的东东。相信网上的资料也不少，不过自己还是捣鼓了半天才弄好的。说道联合仿真，当时避免不了编译xilinx的各种库，即使现在用到不到，以后也是要用到的哇。。首先就的从这里下手。我这个新手肯定喜欢图形界面的编译工作的，所以第一步：Xilinx ISE Design Suite 14.2 -> ISE Design tools-> 32bit tools-》Simulation Library Compilation Wizard.选定ModelSim 的版本，以及指定ModelSim 的安装路径，选择Both VHDL and Verilog，选择支持哪些系列的芯片，看自己需要增减，我还是全选上了，免得粗什么岔子，然后就是选择时序和功能仿真的库，我也都选上了。指定编译完后的库存放位置，这里作者在modelsim 安装目录下新建了xilinx_lib 的文件夹，并指定到这里。（注意不要指向带空格的路径），这个最好自己指定文件夹，不然默认的文件夹用的宏定义那种的方式，貌似不止一个。感觉有点麻烦，然后编译，坐等编译结束吧。第二步：、右键打开modelsim 目录下的modelsim.ini 文件，先将其“只读”属性去掉。然后用记事本打开。在[Library

vhdl: Xilinx code error

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问题 We get this error set: Line 23: Mismatch in number of elements assigned in conditional signal assignment Line 23: Expression has 1 elements ; expected 7 With this code, line 23 is Q_out <= "1111110" when Q_in = "0000" else library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity decoder is Port ( Q_in : in UNSIGNED (3 downto

bit to bit xor with same input vector in vhdl

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问题 I want to do bit by bit xor with same input vector like: input(0) xor input(2) xor input(3) up to input(187) . The answer I get is like: output(0) downto output (94) This means I have to do xor successively. If I have 10 input bits, the last answer I get is 5 bit output. Its very difficult and not a good approach to write the whole vector. Does anyone knows how to write a efficient code of this in vhdl? I have a idea how to do it. First extract even index bits, then odd index bits and do xor

bit to bit xor with same input vector in vhdl

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Is there anyway to read through a file multiple times in vhdl using std textio?

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问题 I am trying to understand how reading a file works in vhdl if I open a file, read through it, test for end of file, close the file and then re open that file and then start to read again will it start from the beginning of the file? many thanks 回答1: Look to the authority on the VHDL language for your answer. IEEE Std 1076-2008 5.5 File types 5.5.1 General A file type definition defines a file type. File types are used to define objects representing files in the host system environment. The

Is there anyway to read through a file multiple times in vhdl using std textio?

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Substatemachine

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问题 I have a FSM with 5 states. 3 of them are designed via sub-FSM(UML Pattern). For implementation in VHDL there are 2 ways, imho, to do that: Summarize them into one, so I have a documentation with sub-FSM's and a product with one big FSM. Build one FSM with all states. For every state which have a sub-FSM build a standalone FSM with enable signals from the big one. This is no question about what's better, I think both ways have their advantages and disadvantages. But which way is more "clean"

VHDL and FPGA's

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问题 I'm relatively new to the FPGA sceen and was looking to get experience with them and VHDL. I'm not quite sure what the benefit would be over using a standard MCU but looking for experience since many companies are looking for it. What would be a good platform to start out on and get experience for not to much money. Ive been looking and all I can find are 200 - 300 dollar boards if not 1000's. What should one look for in an FPGA development board, I hear high speed peripheral interfaces, and

Confusion between Behavioural and Dataflow model Programs in VHDL

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问题 I'm using the textbook "VHDL: Programming By Example" by Douglas L Perry, Fourth Edition. He gave an example of the Dataflow programming model in page 4: Code I: ENTITY mux IS PORT ( a, b, c, d : IN BIT; s0, s1 : IN BIT; x, : OUT BIT); END mux; ARCHITECTURE dataflow OF mux IS SIGNAL select : INTEGER; BEGIN select <= 0 WHEN s0 = ‘0’ AND s1 = ‘0’ ELSE 1 WHEN s0 = ‘1’ AND s1 = ‘0’ ELSE 2 WHEN s0 = ‘0’ AND s1 = ‘1’ ELSE 3; x <= a AFTER 0.5 NS WHEN select = 0 ELSE b AFTER 0.5 NS WHEN select = 1