hdl

问题 I am pretty new to Verilog, but would like to understand it properly. Currently I am making TxRx on FPGA. I noticed that my code is consuming huge amount of logic, although it should not be like that. So I did not wrote my code properly. I know where is mistake, obviously my for loop is making parallelization of expressions (especially because this for loop is nested into another for loop). What would be right way to write code to avoid this. The code is working but it is not efficient. Feel

问题 I know that if I am outputting a binary file in verilog, then I can use the following verilog IO standard function: $fwrite(fd,"%u",32'hABCDE124); But the above command writes 4-byte data into the file. What if the binary data that I want to write is only one-byte, two-bytes or three-bytes? How can I do this? For example, I know the following won't do what I want: $fwrite(fd,"%u",8'h24); $fwrite(fd,"%u",16'hE124); $fwrite(fd,"%u",24'hCDE124); Is there any way that I can write a non 4-byte

问题 I am having trouble understanding why my code have a latch logic [1:0] lru_list [0:3]; always_comb begin if(reset) begin lru_list[0] = 0; lru_list[1] = 0; lru_list[2] = 0; lru_list[3] = 0; end else begin case({access, update, access_index_i < 4}) 3'b101: begin lru_list[0] = lru_list[0] + 1; lru_list[1] = lru_list[1] + 1; lru_list[2] = lru_list[2] + 1; lru_list[3] = lru_list[3] + 1; lru_list[access_index_i] = 0; end 3'b011: begin lru_list[0] = lru_list[0]; lru_list[1] = lru_list[1]; lru_list[2

问题 I trying to run the following and I receive this error: Here's the Verilog code: module needle( input referrence,input penalty,output index[7:0]); //inout input_itemsets; //input referrence; //input penalty; //output index; parameter max_cols=8; // wire index[7:0]; wire referrence; wire penalty; //wire input_itemsets; genvar i,idx; generate for( i = max_cols-4 ; i >= 0 ; i=i-1) for( idx = 0 ; idx <= i ; idx=idx+1) begin assign index[i] = (idx + 1) * max_cols + (i + 1 - idx); //assign index =

问题 module fronter ( arc, length, clinic ) ; input [7:0] arc; output reg [7:0] length ; input [1:0] clinic; input en0, en1, en2, en3; // 11 // clock generator is here g_cal A( en0) ; g_cal B( en1) ; g_cal C( en2) ; g_cal D( en3) ; always @( negedge arc, posedge clk ) case ( clinic ) 2'b00 : { en3, en2, en1, en0 } = 4'b0001; // 23 2'b01 : { en3, en2, en1, en0 } = 4'b0010; // 24 2'b10 : { en3, en2, en1, en0 } = 4'b0100; // 25 2'b11 : { en3, en2, en1, en0 } = 4'b1000; // 26 default : { en3, en2, en1

问题 can you say what is the meaning of that always @ * Is there any possible side effects after using that statement ? 回答1: It's just a shortcut for listing all of the wires that the always block depends on. Those wires are the "sensitivity list". One advantage of using it is that synthesized code is unlikely to care what you put in the sensitivity list (other than posedge and negedge ) because the wires will be "physically" connected together. A simulator might rely on the list to choose which

问题 In VHDL I want to take a 14 bit input and append '00' on the end to give me a 16 bit number which is the 14 bit input multiplied by 4 and then put this into a 17 bit signed variable such that it is positive (the input is always positive). How should I go about this? like this? shiftedInput <= to_signed('0' & input & '00', 17); Or maybe like this? shiftedInput <= to_signed(input sll 2, 17); Or this? shiftedInput <= to_signed(input & '00', 17); Does it see that the std_logic_vector it's getting

问题 I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module. As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench. The idea I had was to launch one simulation for each configuration. I thought about generating a simulation script that will launch the simulation for each delay configuration. The problem is that I cannot manage to override

问题 New to Verilog and trying to figure out the basics of assiging wires based on combination logic. I have: wire val; wire x; wire a; wire b; always @* begin if(val == 00) I want to assign x = a if(val == 01) I want to assign x = b end where a and b are wires with values - and x is a wire going into a register. If you can please point me in the right direction to what I need to change, it would be much appreciated. Thank You. 回答1: First thing to ask is: are you trying to use those wires as

问题 I'm trying to make a buffer to hold 16, 16-bit wide instructions for a small CPU design. I need a way to load instructions into the buffer from my testbench. So I wanted to use an array of std_logic_vectors to accomplish this. However, I am getting a syntax error and I'm not sure why (or if I'm allowed to do this in VHDL for that matter). The syntax error is at the line where I declare instructions library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity instruction_buffer