If statement and assiging wires in Verilog

问题

New to Verilog and trying to figure out the basics of assiging wires based on combination logic.

I have:

wire val;
wire x;
wire a;
wire b;

always @*
begin

if(val == 00)
 I want to assign x = a
if(val == 01)
 I want to assign x = b

end

where a and b are wires with values - and x is a wire going into a register.

If you can please point me in the right direction to what I need to change, it would be much appreciated.

Thank You.

回答1:

First thing to ask is: are you trying to use those wires as inputs? Or are you using those as connections? Second thing: Do you want a synthesizable code? And you cant assign wires inside an always block, you have to use reg

So an opinion is:

//**************************************************************************************
module(a, b, out); //You have to define an interface, and all Verilog modules starts with module 
input val[1:0]; //you have to use [] in order to indicate the length. In this case 2 bits, since you want to ask for 00;
input a;
input b;
output out;

reg x;

always @* //NOTE: You are describing combo logic, since there is no clock signal
begin

      if(val == 2'b00)
        x = a;
      else if(val == 2'b01)
        x = b;
      else 
        x = 0; //If you are describing combo logic, you have to cover ALL val cases, in                     order to evade latches

end

assign out = x; //This is how you assign values in Verilog

endmodule

回答2:

wires can only be assigned by assign statements, which can not be used with if statements. If you change x to reg type, then you will be able to assign it in an always block.

This will synthesize exactly the same, a common misconception is that a reg type variable implies a register, but it just changes the way the value is assigned.

Alternatively, you can use an assign statement with ternary operator ?:, if you want it to remain as a wire type:

assign x = (val==0) ?   a : 
           (val==1) ?   b : 
                      'bx ;

回答3:

First of all, I didn't notice any input or output ports in your module. Nor did I notice a proper module declaration with a beginning and end.

However, assuming your module is defined as follows, with inputs a,b, and val and output x:

module myfirstmodule (
  input       a,
  input       b,
  input [1:0] val,
  output      x
);

// Assign a or b to x based upon val
assign x = (val == 2'b00) ? a : 
           (val == 2'b01) ? b :
           0; // Since val can take on values 00,01,10, and 11, we define all possible cases

endmodule

The assign statement serves as a conditional block like an if statement you are probably used to in popular programming languages such as C or C++.

The assign operator works as such: