hdl

问题 Are there any fixed point libraries in Chisel HDL which could be used to perform basic arithmetic operations such as add, subtract, multiply and divide? 回答1: I believe a Fixed class is under active development. Take a look at Fixed.scala in the Chisel repo. 来源： https://stackoverflow.com/questions/35237958/fixed-point-arithmetic-in-chisel-hdl

问题 This statement: reg [7:0] register_file [3:0] = 0; Produces this error: Error (10673): SystemVerilog error at simpleprocessor.v(27): assignments to unpacked arrays must be aggregate expressions First of all I am using Verilog, not SystemVerilog, so why is it giving me a SystemVerilog error? Second of all, what is the cause of this error, and how can I fix it? I am using it in my desgin of a very rudementary processor to represent the internal working registers as a multidemmnsional array of

问题 I want to implement a reciprical block on Verilog that will later be synthesized on an FPGA. The input should be a signed 32 bit wordlength with a 16 bit fraction length. The output should have the same format. Example input : x ---> output ---> 1/x I have solved the problem using the inbuilt IP core divider. I'm wondering if there is an elegant/altenative way of solving this by for example by bit shifting or 2's complement with some xor grinds. I have used the IP core to implement the

问题 I have written a Verilog code, this code to describe a combinational module. I used a blocking assignment. in other parts, there is must use a nonblocking assignment. can I use a delay in the blocking assignment to be alternative to a nonblocking assignment... I don't want to mix these two assignments in one module `timescale 1ns / 1ps module buffer(datain1,datain2,datain3,datain4, s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12, src_out1,src_out2,src_out3, src_out4,src_out5,src_out6, src_out7,src

问题 I designed a primality testing for Rabin Miller algorithm in behavioral type. I used functions to create my modules. Unfortunately, when I tried to synthesize it by my Altera Kit via Quartus, I realized that function are not synthesize. Here I will write my whole program, and I really need you help to give me at least some hints to change it to structural as it is my senior design project. Here is my program: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity

问题 Recently I asked here, how to generate random numbers in hardware and was told to use an LFSR. It will be random but will start repeating after a certain value. The problem is that the random numbers generated are so predictable that the next value can be easily guessed. For example check the simulation below: The next "random" number can be guessed by adding the previous number with a +1 of itself. Can someone please verify if this is normal and to be expected. Here is the code I used for

问题 I would like to write an integer (variable num) on a file (write.txt). Here my code but obviously it does not work. Any suggestion? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.MATH_REAL.ALL; library std; use std.textio.all; entity file_handle is end file_handle; architecture Behavioral of file_handle is begin process variable line_var : line; file text_var : text; variable num : integer := 40; begin file_open(text_var,"C:\Users\Tommy\Desktop\write.txt", write_mode); write(line_var,

问题 I get the following error when compiling RISCV VERILOG HDL on Xilinx ISE: It says "Unsupported System Function Call" in the following code at line 296 in module vscale_pipeline 295: ifndef SYNTHESIS 296: PC_WB <= $random; 回答1: Some synthesis tools define the SYNTHESIS macro so that it is easier to skip non-synthesizable code in synthesis using `ifdef SYNTHESIS ... `endif blocks, as is done in this code. Xilinx XST does not define this macro by default, so you have to configure XST manually to

问题 I'm currently writing an AXI4 master that is supposed to support AXI4 Lite (AXI4L) as well. My AXI4 master is receiving data from a 16-bit interface. This is on a Xilinx Spartan 6 FPGA and I plan on using the EDK AXI4 Interconnect IP, which has a minimum WDATA width of 32 bits. At first I wanted to use narrow burst, i.e. AWSIZE = x"01" (2 bytes in transfer). However, I found that Xilinx' AXI Reference Guide UG761 states "narrow bursts [are] supported but [...] not recommended." Unaligned

问题 I want write an alternative of the if, I have following if statement. if val1(1)&val1(0) < val2(1)&val2(0) then r:="10"; else if val1(1)&val1(0) = val2(1)&val2(0) then r:="00"; else r:="01"; end if; end if; And I want it to change to following. s:=((data1(9)&data1(8)) < (data2(9)&data2(8)))?"01":(((data1(9)&data1(8)) = (data2(9)&data2(8)))?"00":"01"); But the compiler gives me following error. "# Error: COMP96_0015: min: (111, 49): ';' expected." How can I resolve this? Thanks. 回答1: Question: