hdl

this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four digit seven segment display on a BASYS2 board. I have checked to make sure that 0 enables the signal and that I have the ports mapped correctly. I believe the error is within my multiplexing logic since I am only able to display a single digit. I'm new to Verilog (am used to C) and would appreciate any suggestions. Thanks `timescale 1ns / 1ps module main (clock, AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE, CF, CG, CDP); //USED FOR SEVEN SEG input clock; output AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE,

I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module. As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench. The idea I had was to launch one simulation for each configuration. I thought about generating a simulation script that will launch the simulation for each delay configuration. The problem is that I cannot manage to override the parameters of the module with the values retrieved from the command-line. I used $value$plusargs(

New to Verilog and trying to figure out the basics of assiging wires based on combination logic. I have: wire val; wire x; wire a; wire b; always @* begin if(val == 00) I want to assign x = a if(val == 01) I want to assign x = b end where a and b are wires with values - and x is a wire going into a register. If you can please point me in the right direction to what I need to change, it would be much appreciated. Thank You. First thing to ask is: are you trying to use those wires as inputs? Or are you using those as connections? Second thing: Do you want a synthesizable code? And you cant

I am trying to write a BCD Adder in Verilog, but I am having trouble with one of the modules. Specifically, the adder that takes two BCD digits and adds them. So, the idea is if the sum of the two digits is less than or equal to nine, then it is correct. However, if it is greater, then an offset of 6 has to be added. Here is my Verilog code so far: module DIGITADD( input [3:0] IN_A, input [3:0] IN_B, input CIN, output reg COUT, output reg [3:0] SUM ); wire s2, c2; always @ ( * ) begin assign {c2, s2} = IN_A + IN_B + CIN; if(s2 <= 9 && c2 == 0) begin assign {COUT, SUM} = {c2, s2}; end else if(

I'm trying to make a buffer to hold 16, 16-bit wide instructions for a small CPU design. I need a way to load instructions into the buffer from my testbench. So I wanted to use an array of std_logic_vectors to accomplish this. However, I am getting a syntax error and I'm not sure why (or if I'm allowed to do this in VHDL for that matter). The syntax error is at the line where I declare instructions library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity instruction_buffer is port ( reset : in std_logic; instructions : in array(0 to 15) of std_logic_vector(15 downto 0);

I am trying to write a register file in VHDL. The file contains 16 64-bit registers. Each cycle, two registers are read and one register is written (given that writing is enabled). There should be a data bypass (forwarding) so that the value just written is forwarded directly to the output if we are reading and writing to/from the same register in a single cycle. My idea was to write on the rising edge and read on the falling edge of the clock in order to complete this in one cycle. However, my design isn't working (not that I expected it to since I don't believe that checking for a falling

Assuming I have a register reg [15:0] my_reg , which contains a 16-bit signed sample: How do I convert the sample from signed to unsigned? I have read this Wikipedia article , and am aware of the 2-bit complement for signed numbers, but how do I perform this conversion in Verilog efficiently? (I don't know if my_reg is positive or negatve, and it changes in every clock cycle = I receive a new sample on every positive clock edge). The ultimate goal (to add a little bit of context) is to implement a digital FPGA built-in automatic gain control (AGC). EDIT: as suggested I have split the two