not a valid l-value - verilog compiler error

问题

module fronter ( arc, length, clinic ) ;
 input [7:0] arc;
 output reg [7:0] length ;

 input [1:0] clinic;
 input en0, en1, en2, en3; // 11

 // clock generator  is here

 g_cal A( en0) ;
 g_cal B( en1) ;
 g_cal C( en2) ;
 g_cal D( en3) ;

always @( negedge arc, posedge clk )
  case ( clinic ) 
    2'b00 : { en3, en2, en1, en0 } = 4'b0001;    // 23
    2'b01 : { en3, en2, en1, en0 } = 4'b0010;    // 24
    2'b10 : { en3, en2, en1, en0 } = 4'b0100;    // 25
    2'b11 : { en3, en2, en1, en0 } = 4'b1000;    // 26
    default : { en3, en2, en1, en0 } = 4'bxxxx;  // 27
  endcase

// I am trying to change value of en to call corresponding intance with that 
//corresponding en value

endmodule

module g_cal ( en ) ;

 input en ;
 // some other jobs, calling another instances after making some job

endmodule

when I compile, compiler gives me ;

verilog.v:23: error: en0 is not a valid l-value in Numerator.
verilog.v:11:      : en0 is declared here as wire.
verilog.v:24: error: en1 is not a valid l-value in Numerator.
verilog.v:11:      : en1 is declared here as wire.
verilog.v:25: error: en2 is not a valid l-value in Numerator.
verilog.v:11:      : en2 is declared here as wire.
verilog.v:26: error: en3 is not a valid l-value in Numerator.
verilog.v:11:      : en3 is declared here as wire.
verilog.v:27: error: en3 is not a valid l-value in Numerator.
verilog.v:11:      : en3 is declared here as wire.
segmentation fault

How can I fix it ? Why it gives error?

EDIT: I have solved problem as ;

   // I erased that line "input en0, en1, en2, en3; // 11"

 // clock generator  is here

 g_cal A(  1'b0) ;
 g_cal B(  1'b0) ;
 g_cal C(  1'b0) ;
 g_cal D(  1'b0) ;

always @( negedge arc, posedge clk )
/* erasing all those line 
 case ( clinic ) 
    2'b00 : { en3, en2, en1, en0 } = 4'b0001;    // 23
    2'b01 : { en3, en2, en1, en0 } = 4'b0010;    // 24
    2'b10 : { en3, en2, en1, en0 } = 4'b0100;    // 25
    2'b11 : { en3, en2, en1, en0 } = 4'b1000;    // 26
    default : { en3, en2, en1, en0 } = 4'bxxxx;  // 27
  endcase

I will use if and else structure, and calling corresponding instance with 1'b1*/

 // I am trying to change value of en to call corresponding intance with that 
//corresponding en value

endmodule

回答1:

You're trying assign to an input (which is bad). Change input en0, en1, en2, en3; to output reg en0, en1, en2, en3;. The reg is necessary since you are assigning to that variable within a procedural block (ie, an always or initial). The "not a valid l-value" message is trying to tell you this.

Also, I'm assuming that the 11, 23, 24, etc are stray line numbers from a copy-paste...

回答2:

Problem has solved when I write ;

reg en0, en1, en2, en3 ;

initial begin 
  en0 <= 1'b0; en1 <= 1'b0; 
  en2 <= 1'b0; en3 <= 1'b0;
end

g_cal A(  en0) ;
g_cal B(  en1) ;
g_cal C(  en2) ;
g_cal D(  en3) ;

@Marty have emphasized important thing "The reg is necessary since you are assigning to that variable within a procedural block (ie, an always or initial)."

来源：https://stackoverflow.com/questions/5636055/not-a-valid-l-value-verilog-compiler-error

标签

verilog

hdl

digital-logic