问题
I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module.
As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench.
The idea I had was to launch one simulation for each configuration.
I thought about generating a simulation script that will launch the simulation for each delay configuration. The problem is that I cannot manage to override the parameters of the module with the values retrieved from the command-line.
I used $value$plusargs("ARG=%d",val) and the fact that val is a variable is incompatible with the later defparam.
The perfect thing would be to create a define, or a localparam from the command-line argument but I did not find anything about it in my research.
I am also open to any suggestion about another way to doing these simulation, maybe more efficiently, because I think that this will be quite long to do it that way.
PS: To avoid recompiling and re-lauching the simulator for each configuration I also thought about re-instantiating the tested module in each case. I however do not think that it is possible with (system)verilog.
回答1:
Modelsim/Questa allows you to override parameters from the simulation command line, but does so as some cost in simulation performance. Look for the vsim -Gparamname option.
In your case, it would be much better if you could write your modules using variables for these delays instead of parameters, then use $value$plusargs to set them directly.
来源：https://stackoverflow.com/questions/36423219/defining-parameters-from-command-line-in-systemverilog-simulation