问题
Following the answer about assembly registers' sizes:
First, what sizes are
eax,ax,ahand their counterparts, in the 64-bit architecture? How to access a single register's byte and how to access all the 64-bit register's eight bytes?I'd love attention for both x86-64 (x64) and Itanium processors.
Second, what is the correct way to use the four registers for holding the first four parameters in function calls in the new calling convention?
回答1:
With the old name all registers remain the same size. To access 64-bit registers you use the new name with R-prefix such as rax, rbx...
Register names don't change so you just use the byte registers (al, bl, cl, dl, ah, bh, ch, dh) for the LSB and MSB of ax, bx, cx, dx like before.
There are also 8 new registers called r8-r15. You can access their LSBs by adding the suffix b (or l if you're using AMD). For example r8b, r9b... You can also use the LSB of esi, edi, esp, ebp by the names sil, dil, spl, bpl with the new REX prefix, but you cannot use it at the same time with ah, bh, ch or dh.
Likewise the new registers' lowest word or double word can be accessed through the suffix w or d.
What are the names of the new X86_64 processors registers?
Regarding the calling convention, on a specific system there's only one convention1.
On Windows:
- RCX, RDX, R8, R9 for the first four integer or pointer arguments
- XMM0, XMM1, XMM2, XMM3 for floating point arguments
1Since MSVC 2013 there's also a new extended convention on Windows called __vectorcall.
On Linux and other systems that follow System V AMD64 ABI, more arguments can be passed on registers which may make function calling faster.
- The first six integer or pointer arguments are passed in registers RDI, RSI, RDX, RCX, R8, and R9
- Floating-point arguments are passed in XMM0 through XMM7
x86_64 calling conventions
Those are the most basics of x86_64. You should also read this
There's also a convention used in Plan 9 where
- All registers are caller-saved
- All parameters are passed on the stack
- Return values are also returned on the stack, in space reserved below (stack-wise; higher addresses on amd64) the arguments.
In fact Plan 9 was always a weirdo. For example it forces a register to be 0 on RISC architectures without a hardware zero register. x86 register names on it are also consistent across 16, 32 and 64-bit x86 architectures, operand size is indicated by mnemonic suffix. If you're curious about it read
- A Manual for the Plan 9 assembler
- https://nelhagedebugsshit.tumblr.com/post/84342207533/things-i-learned-writing-a-jit-in-go
OTOH Itanium is a completely different architecture and has no relation to x86_64 whatsoever. It's a pure 64-bit architecture so all normal registers are 64-bit, no 32-bit or smaller version available. There are a lot of registers in it:
- 128 general-purpose integer registers r0 through r127, each carrying 64 value bits and a trap bit. We'll learn more about the trap bit later.
- 128 floating point registers f0 through f127.
- 64 predicate registers p0 through p63.
- 8 branch registers b0 through b7.
- An instruction pointer, which the Windows debugging engine for some reason calls iip. (The extra "i" is for "insane"?)
- 128 special-purpose registers, not all of which have been given meanings. These are called "application registers" (ar) for some reason. I will cover selected register as they arise during the discussion.
- Other miscellaneous registers we will not cover in this series.
https://blogs.msdn.microsoft.com/oldnewthing/20150727-00/?p=90821
Read more on What is the difference between x64 and IA-64?
来源：https://stackoverflow.com/questions/20637569/assembly-registers-in-64-bit-architecture