问题
I'm trying to count the number of cache hit at different levels (L1, L2 and L3) of cache for a program on Intel Haswell processor.
I wrote a program to count the number of L2 and L3 cache hits by monitoring the respective events. To achieve that, I checked Intel x86 Software Development Manual and used the cache_all_request event and cache_miss event for L2 and L3 cache. However, I didn't find the events for L1 cache. Maybe I missed something?
My questions are:
Which Event Number and UMASK value I should use to count the L1 cache hit events?
Clarifications*
1) The final goal I want to achieve is to upper bound a program's execution time when all cache hits of the program become cache misses. If I can count the number of cache hit requests, I can treat them as cache miss and calculate the increased execution time;
2) I checked the event MEM_LOAD_UOPS_RETIRED.L1_ HIT in Intel SDM, it says "Retired load uops with L1 cache hits as data sources.". I'm not sure if 1 uops takes 1 cycle. Is there any reference about how to transfer uops to cycles?
3) It will be better to count both loads and stores. (I can tolerate not counting store requests though.)
Thank you so much for your help!
来源：https://stackoverflow.com/questions/49042275/intel-pmu-event-for-l1-cache-hit-event