用VHDL语言描述全减器

图一全减器原理图

图一是用VHDL语言描述全减器的原理图。全减器依然用到了例化语句。其程序如下:

library ieee;
use ieee.std_logic_1164.all;
entity f_jq is
port(x,y,sub_in:in std_logic;
diffr,sub_out:out std_logic
);
end;
architecture fjq of f_jq is
component BJQ
port(a,b:in std_logic;
d,s:out std_logic
);
end component;
component or2a
port(A,B:in std_logic;
C:out std_logic
);
end component;
signal net1,net2,net3 :std_logic;
begin
u1:BJQ port map(a=>x,b=>y,d=>net1,s=>net2);
u2:BJQ port map(a=>net1,b=>sub_in,d=>diffr,s=>net3);
u3:or2a port map(A=>net3,B=>net2,C=>sub_out);
end architecture fjq;

其中用到例化语句半减器，其程序如下:

library ieee;
use ieee.std_logic_1164.all;
entity BJQ is
port(a,b:in std_logic;
d,s:out std_logic
);
end;
architecture bhv of BJQ is
begin
d<=a xor b;
s<=(not a)and b;
end architecture bhv;

其半减器原理图如图二所示。

例化语句或门程序如下：

library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(
A,B:in std_logic;
C:out std_logic
);
end entity or2a;
architecture one of or2a is
begin
c<=a or b;
end architecture one;

其原理图如图三所示: