Reverse bit order on VHDL
问题 I'm having trouble doing something like b(0 to 7) <= a(7 downto 0) when I compile it with ghdl, I have an order error. The only way I have found to make my circuit work is the following: library ieee; use ieee.std_logic_1164.all; entity reverser is port( a: in std_logic_vector(7 downto 0); y: out std_logic_vector(7 downto 0); rev: in std_logic ); end reverser; architecture rtl of reverser is signal b: std_logic_vector (7 downto 0); begin b(7) <= a(0); b(6) <= a(1); b(5) <= a(2); b(4) <= a(3);