vhdl

Reverse bit order on VHDL

▼魔方 西西 提交于 2019-12-31 10:18:28
问题 I'm having trouble doing something like b(0 to 7) <= a(7 downto 0) when I compile it with ghdl, I have an order error. The only way I have found to make my circuit work is the following: library ieee; use ieee.std_logic_1164.all; entity reverser is port( a: in std_logic_vector(7 downto 0); y: out std_logic_vector(7 downto 0); rev: in std_logic ); end reverser; architecture rtl of reverser is signal b: std_logic_vector (7 downto 0); begin b(7) <= a(0); b(6) <= a(1); b(5) <= a(2); b(4) <= a(3);

Integer to String goes wrong in Synthesis (Width Mismatch)

戏子无情 提交于 2019-12-31 05:29:07
问题 I am trying to convert a integer to string (using integer'image(val) ) and either pad or limit it to a specific length. I have made this function which does the job just fine when I use a report statement and simulate. function integer2string_pad(val: integer; stringSize: integer) return string is variable imageString: string(1 to integer'image(val)'length); variable returnString: string(1 to stringSize); begin imageString := integer'image(val); -- Are we smaller than the desired size? if

VHDL “For” Loop Null Range

白昼怎懂夜的黑 提交于 2019-12-31 05:14:33
问题 I've been stuck at this problem for some hours now, and it seems I can't find the solution by searching i.e. didn't find anything here or on Google. Here's my piece of code: LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std; USE work.arrays.ALL; ENTITY parallel IS PORT (clk:IN std_logic; text:IN INT_ARRAY(119 DOWNTO 0); result:OUT INT_MATRIX_2D); END parallel; ARCHITECTURE arch OF parallel IS COMPONENT unit_comparator IS PORT (letter:IN integer; difference:OUT integer); END

how to delay a signal for several cycles in vhdl

被刻印的时光 ゝ 提交于 2019-12-31 02:56:06
问题 How to delay signal for a given number of cycles in VHDL? Number of cycles is given as a generic. Any other options instead of process(CLK) is begin if rising_edge(CLK) then a_q <= a; a_q_q <= a_q; a_q_q_q <= a_q_q; -- etc end if; end process; ? 回答1: Create an 1-d array (let's call it a_store ) of the appropriate type of signal with the length of the array related to the number of cycles. This may mean you have to create a new type for the array unless there's already a vector type you can

Delta Cycles and Waveforms

非 Y 不嫁゛ 提交于 2019-12-30 05:02:06
问题 Can anyone explain how delta cycles affect waveforms simulated by VHDL? I understand that it has to do with how VHDL determines precedence but I'm not exactly sure how. 回答1: You won't find the information in the VHDL standard (IEEE Std 1076-2008), and what delta cycles do are not widely understood (there's a hint here about how much you actually need to know as a language user, an abstract knowledge can suffice). Delta cycles precede VHDL. You can find references on the Internet dating back

Read textfile in VHDL testbench

与世无争的帅哥 提交于 2019-12-29 09:59:27
问题 I have a file source.txt , it looks like this: 00660066006700670067006800680069006B006D006E 00660066006700670067006800680069006B006D006E 00660066006700670067006800680069006B006D006E 00660066006700670067006800680069006B006D006E 00660066006700670067006800680069006B006D006E 0065006500660067006700690069006A006B006C006E 00650065006600670067006700680069006A006C006D 00650065006600670067006600660068006A006B006D 006500650066006700670065006600670069006B006D 00650065006600670067006600670068006A006C006D

2D Unconstrained Nx1 Array

若如初见. 提交于 2019-12-29 09:29:04
问题 I'm trying to create a flexible array of constants. I want to use a 2D array which may sometimes be for example a 2x1, 2x2, 3x2 array etc. For example: type int_2d_array is array (integer range<>, integer range<>) of integer; constant M : positive := 2; constant nMax : positive := 1; constant n : int_2d_array(M - 1 downto 0, nMax - 1 downto 0) := ( (1) , (2) ); -- wrong error: type int_2d_array does not match with the integer literal If I do this, it doesn't complain: type int_2d_array is

How to read from a specific line from a text file in VHDL

匆匆过客 提交于 2019-12-29 09:04:29
问题 I am doing a program in VHDL to read and write data. My program has to read data from a line, process it, and then save the new value in the old position. My code is somewhat like: WRITE_FILE: process (CLK) variable VEC_LINE : line; file VEC_FILE : text is out "results"; begin if CLK='0' then write (VEC_LINE, OUT_DATA); writeline (VEC_FILE, VEC_LINE); end if; end process WRITE_FILE; If I want to read line 15, how can I specify that? Then I want to clear line 15 and have to write a new data

How to read from a specific line from a text file in VHDL

老子叫甜甜 提交于 2019-12-29 09:04:13
问题 I am doing a program in VHDL to read and write data. My program has to read data from a line, process it, and then save the new value in the old position. My code is somewhat like: WRITE_FILE: process (CLK) variable VEC_LINE : line; file VEC_FILE : text is out "results"; begin if CLK='0' then write (VEC_LINE, OUT_DATA); writeline (VEC_FILE, VEC_LINE); end if; end process WRITE_FILE; If I want to read line 15, how can I specify that? Then I want to clear line 15 and have to write a new data

Difference between mod and rem operators in VHDL?

流过昼夜 提交于 2019-12-29 04:42:07
问题 I came across these statements in VHDL programming and could not understand the difference between the two operators mod and rem 9 mod 5 (-9) mod 5 9 mod (-5) 9 rem 5 (-9) rem 5 9 rem (-5) 回答1: A way to see the different is to run a quick simulation in a test bench, for example using a process like this: process is begin report " 9 mod 5 = " & integer'image(9 mod 5); report " 9 rem 5 = " & integer'image(9 rem 5); report " 9 mod (-5) = " & integer'image(9 mod (-5)); report " 9 rem (-5) = " &