vhdl

Binary serial adder - VHDL

吃可爱长大的小学妹 提交于 2019-12-25 18:33:36
问题 I'm trying to design a 32bit binary serial adder in VHDL, using a structural description. The adder should make use of a full adder and a d-latch. The way I see it is: Full adder: architecture Behavioral of FullAdder is begin s <= (x xor y) xor cin; cout <= (x and y) or (y and cin) or (x and cin); end Behavioral; D-Latch: architecture Behavioral of dLatch is begin state: process(clk) begin if(clk'event and clk = '1') then q <= d; end if; end process; end Behavioral; Serial adder: add: process

How to use the Xilinx Division IP Core

回眸只為那壹抹淺笑 提交于 2019-12-25 18:32:42
问题 I am writing code in VHDL to be synthesised onto a XilinX FPGA. I typically use GHDL to simulate my testbenches. I need to make use of the XilinX division core in order to divide by a variable however I am not sure how to do this as there appear to be no examples in the XilinX documentation. Do I have to use the XilinX software to generate the VHDL component for the divider? Or does XilinX implicitly understand that divider means using the IP core? If my 2nd statement is true how would I go

VHDL Selection machine error in port map

时光毁灭记忆、已成空白 提交于 2019-12-25 17:21:08
问题 I get this error: # Error: COMP96_0100: data_reg.vhd : (156, 35): Actual parameter type in port map does not match the port formal type "Allin". # Error: COMP96_0100: data_reg.vhd : (158, 1): Actual parameter type in port map does not match the port formal type "Fout". # Error: COMP96_0100: data_reg.vhd : (162, 1): Actual parameter type in port map does not match the port formal type "D". # Error: COMP96_0100: data_reg.vhd : (163, 1): Actual parameter type in port map does not match the port

VHDL - Arbitrarily Unconnected components

六眼飞鱼酱① 提交于 2019-12-25 17:05:37
问题 Using Lattice Diamond 3.6.0.83.4 MachX03 starter kit After a lot of struggling I figured out why many of my inputs were unconnected. It came down to some bad assignments in a debouncer module. After I cleaned up the debouncer, everything worked fine, except for a handful of inputs. For some reason, these inputs refuse to connect to anything. I can't find much in the code because it's a lot of copy-pasting all over the place. I've exhaustively reviewed what I've done so it makes no sense to me

Square Waveform Generation in VHDL

人盡茶涼 提交于 2019-12-25 14:27:29
问题 I'm working on a stopwatch project in VHDL but I don't know how to make the CLK square waveform of the counter? Please help. Here is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity Circuit is Port ( CLK : in STD_LOGIC := '0'; CLR : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (5 downto 0)); end Circuit; architecture Behavioral of Circuit is signal s: STD_LOGIC_VECTOR := "000000"; begin process (CLK, CLR) begin if rising_edge(CLK) then if CLR = '1' OR s =

VHDL Error (10818): Can't infer register

荒凉一梦 提交于 2019-12-25 14:00:43
问题 So I am a beginner in VHDL and I am trying to code a MIPS processor for a FPGA. The file for the CPU Register is not compiling. It is generating an error code as following Error (10818): Can't infer register for "Reg[0][2]" at cpu_register.vhd(32) because it does not hold its value outside the clock edge library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cpu_register is Port ( Source_Register_Address : in std_logic_vector(4 downto

Why am getting inferred latches?

偶尔善良 提交于 2019-12-25 12:49:08
问题 I am aware that inferred latches occur when not every possible path is defined, but I have made considerations to avoid this in my process: The signal is: signal BothButtons : std_logic_vector (1 downto 0) ; The process is: Signaling : process(button0, button1) begin if (button0= '0') AND (button1 = '0') then BothButtons <= "00"; elsif (button0= '0') AND (button1 = '1') then BothButtons <= "01"; elsif (button0= '1') AND (button1 = '0') then BothButtons <= "10"; elsif (button0= '1') AND

Match Simulation and Post-Synthesis Behavior in VHDL

有些话、适合烂在心里 提交于 2019-12-25 08:28:13
问题 This question is an extension of the another shown here, VHDL Process Confusion with Sensitivity Lists However, having less than 50 Rep points, I was unable to comment for further explanation. So, I ran into the same problem from the link and accept the answer shown. However, now I am interested in what the recommended approach is in order to match simulation with post-synthesis behavior. The accepted answer in the link states that Level Sensitive Latches are not recommended as a solution due

Counter Not Testing As Expected? [VHDL]

淺唱寂寞╮ 提交于 2019-12-25 07:51:29
问题 I'm trying to make a 32 bit counter in VHDL. Below is my code: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY counter32 IS PORT (en, clk, clr: IN STD_LOGIC; count: OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END counter32; ARCHITECTURE rtl OF counter32 IS SIGNAL count_result: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN counter32: PROCESS(clk, clr) BEGIN count <= "00000"; --Initialize counter to all zeroes IF (clr = '0') THEN count_result <= "00000"; ELSIF (clk = '1' and clk'EVENT)

Weird VHDL Behavior

独自空忆成欢 提交于 2019-12-25 07:30:47
问题 In the following VHDL code when i use logical or the code stops working the HD44780LCD crashes but when i remove the logical or and remove one of the holders the code starts to work again. I'm using Xilinx Spartan 3E starter board. In other words when I replace the SendCommand <= Holder(0); with SendCommand <= Holder(0) or Holder(1); The program acts weird and crashes. Here is the code: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all;