Binary serial adder - VHDL
问题 I'm trying to design a 32bit binary serial adder in VHDL, using a structural description. The adder should make use of a full adder and a d-latch. The way I see it is: Full adder: architecture Behavioral of FullAdder is begin s <= (x xor y) xor cin; cout <= (x and y) or (y and cin) or (x and cin); end Behavioral; D-Latch: architecture Behavioral of dLatch is begin state: process(clk) begin if(clk'event and clk = '1') then q <= d; end if; end process; end Behavioral; Serial adder: add: process