vhdl

问题 entity timer is Port ( click : in STD_LOGIC; clear : out STD_LOGIC; t_unlock : out STD_LOGIC); end timer; architecture Behavioral of timer is signal temp2 : integer range 0 to 20 := 0; begin process begin if rising_edge(click) then temp2<=0; clear<='0'; t_unlock<='0'; else temp2<=temp2+1 after 15 ns; end if; if temp2=6 then clear<='1'; elsif temp2=20 then t_unlock<='1'; end if; end process; end Behavioral; I have writted this code.And the complier say: Signal temp2 cannot be synthesized, bad

问题 I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this example here: ... signal x,y,z : bit; ... process (y) begin x<=y; z<=not x; end process; The example says this: If the signal y changes then an event will be scheduled on x to make it the same as y. Also, an event is scheduled on z to make it the opposite of x. The question is, will the value of z be the opposite of y? Of course, the answer is no, because when the second

问题 I resolved the previous error but system is not allowing me to create a new question that's why i am editing the current one. Now i am getting an error in map like this: ERROR:MapLib:979 - LUT6 symbol "Mmux_ac97_sdata_out22" (output signal=Mmux_ac97_sdata_out21) has input signal "Madd_frame_count_lut<1>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. ERROR:MapLib:979 - LUT6 symbol "Mmux_ac97_sdata_out22" (output signal

问题 I resolved the previous error but system is not allowing me to create a new question that's why i am editing the current one. Now i am getting an error in map like this: ERROR:MapLib:979 - LUT6 symbol "Mmux_ac97_sdata_out22" (output signal=Mmux_ac97_sdata_out21) has input signal "Madd_frame_count_lut<1>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. ERROR:MapLib:979 - LUT6 symbol "Mmux_ac97_sdata_out22" (output signal

问题 My code produces the following error when compiling: ERROR:HDLCompiler:439 - "E:/ELECTRONIC ENGINEERING 2/DIGITAL/Resit_Year/Assignment_7_seg/4_Bit_Counter/Bit_Counter/counter_tb.vhd" Line 47: Formal port count_out of mode buffer cannot be associated with actual port count_out of mode out ERROR:Simulator:777 - Static elaboration of top level VHDL design unit counter_tb in library work failed don't know how to fix this. full code: ---------------------------------------------------------------

问题 My code produces the following error when compiling: ERROR:HDLCompiler:439 - "E:/ELECTRONIC ENGINEERING 2/DIGITAL/Resit_Year/Assignment_7_seg/4_Bit_Counter/Bit_Counter/counter_tb.vhd" Line 47: Formal port count_out of mode buffer cannot be associated with actual port count_out of mode out ERROR:Simulator:777 - Static elaboration of top level VHDL design unit counter_tb in library work failed don't know how to fix this. full code: ---------------------------------------------------------------

问题 I dont know why I am getting this error (Error (10482): VHDL error at SWSelectorVHDL.vhd(11): object "select_vector" is used but not declared). Please point out what do I need to change.. Here is my code library ieee; use ieee.std_logic_1164.all; entity SWSelectorVHDL is generic( NUM : std_logic_vector(2 downto 0) := "000" ); port( selector : in select_vector(7 downto 0); rq : in std_logic_vector(7 downto 0); own : out std_logic_vector(7 downto 0) ); end entity SWSelectorVHDL; architecture

问题 I am using Quatus 2 Prime 16.1 Lite version. what i am trying to do as follows, I have compiled float_pkg_c,fixed_pkg_c under ieee_proposed library as in shown in below link in comment. and i am using to_float to convert real variable to std logic vector as follows, phi_c <= to_std_logic_vector( to_float(phi_c_F, float32'high, -float32'low) ); below phi_c_F is a variable which is to be calculated using sin, arcsin of math_real library.and i found operators in math_real non-synthesize, and i

问题 I'm trying to solve some exercises, I have to shift a 8-bit vector named A into 2A (A+A). my soluction for this is: (A(7) and '1') & A(6 downto 0) & '0'; after this I made a two's complement of A in this way: entity complementare is port(a: in std_logic_vector(7 downto 0); b: out std_logic_vector(7 downto 0)); end complementare; architecture C of complementare is signal mask, temp: std_logic_vector(7 downto 0); component ripplecarry8bit is port(a,b: std_logic_vector(7 downto 0); cin: in std

问题 I am working on generating a 40 bit length pulse train. I also must be able to adjust the frequency. I tried to make a new low frequency clock and i make a new counter which counts on it's rising edges and give an high output and terminating after 40 bit. It's not working. I tried some other methods. They are not, too. For example; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.all; entity con40 is port(clk:in std_ulogic; q:out std_ulogic); end entity con40; architecture