vhdl

问题 library ieee; use ieee.std_logic_1164.all; entity basic_shift_register_with_multiple_taps is generic ( DATA_WIDTH : natural := 8 ); port ( clk : in std_logic; enable : in std_logic; sr_one : in std_logic_vector((DATA_WIDTH-1) downto 0); sr_two : in std_logic_vector((DATA_WIDTH-1) downto 0); sr_out : out std_logic_vector(2*(DATA_WIDTH-1) downto 0) ); end entity ; architecture rtl of basic_shift_register_with_multiple_taps is signal sig_out :std_logic_vector(2*(DATA_WIDTH-1) downto 0); variable

问题 I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to create "intelligent" counter triggered by clock with frequency 2 Hz. This counter is built in one state of FSM and is started by pushing a button on DE2 board. Firstly, whole system is in IDLE state and if I push this button, state is changed to COUNTING and counter begin to be incremented and his current value is shown on LED display. After it reach value of modulo, the state COUNTING is

问题 We are implementing an Ethernet MAC controller in VHDL.. To start of, here is a code snippet of my code.. -- next state PROCESS(p_state, phy_start, phy_ctr, phy_clk) BEGIN CASE p_state IS WHEN sIDLE => IF(phy_start = '1' or rising_edge(phy_start)) THEN n_state <= sPRE; ELSIF(phy_start'event AND phy_start='0') THEN n_state <= n_state; ELSE n_state <= sIDLE; END IF; ............ The problem is that my professor told me I associated phy_start as the clock signal where in the rising_edge() must

问题 I am writing a VHDL program on quartus II for a CYCLONE III EP3C25 FPGA and I got an issue. Here are the important part of my program: odata : out std_logic_vector(15 downto 0); signal buf_data : std_logic_vector(255 downto 0); signal nb_word : integer :=0; Process(clk,RST) begin if(RST='0') then nb_word<=0; elsif(clk'event and clk='0') then if(Current_state_w=s2) then if(nb_word<=X"F0") then nb_word<=nb_word+16; else nb_word<=0; end if; end if; end if; end process; Process(clk,RST) begin if

问题 I'm trying to make a shiftregister in vhdl. My issue is when I try to store values in the regisgter. This is the code that's causing trouble: architecture behave of chan_mod is signal adc_shfreg : std_logic_vector(15 DOWNTO 0); signal dac_shfreg : std_logic_vector(15 DOWNTO 0); begin Rcv_adc: process(mclk, reset) begin if rising_edge(mclk) then if (reset = '0') then adc_out <= "0000000000000000"; elsif(chan_on = '1' AND subcycle_cntr = "01" AND chan_sel = '0' AND bit_cntr < 16) then adc

问题 I am trying to read an image file using textio package in vhdl. If i open an .jpg with notepad , i will get some junk data but actually it is ASCII data . Here i am trying to read these ascii data and convert them into bytes. below is my code: library ieee; use ieee.std_logic_1164.all; use std.textio.all; use ieee.std_logic_textio.all; entity file_io is port ( clk: in std_logic; Data: out std_logic_vector(7 downto 0) ); end entity; architecture behav of file_io is signal test_data : std_logic

问题 I have an FSM and it works. The synthesizer, however, complains that there are latches for "acc_x", "acc_y", and "data_out" and I understand why and why it is bad. I have no idea, however, how to rewrite the FSM so the state-part goes to the clocked process. Any ideas where to start from? Here is the code of the FSM: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity storage is port ( clk_in : in std_logic; reset : in std_logic; element_in : in std_logic; data_in : in

问题 I'm designing an Ethernet MAC Controller for Spartan 3E FPGA. IOBs have reached 109%. I still proceeded with the generation of bitstream. I then encountered this error: Too many comps of type "BUFGMUX" found to fit this device. What does this mean? (I'm pretty sure that running the Spartan 3e can run the Ethernet since there is already an IP of Ethernet lite MAC for Spartan 3e. Also, it has more pins than I have in my module. Why does it have then 109% of IOBs?) I also tried commenting the

问题 I have few unsigned, 8bits-wide number that i need to add/subtract together. Below the example: h_tmp <= signed(r4(calc_cnt - 2) + r4(calc_cnt - 1) + r4(calc_cnt) + r4(calc_cnt + 1) + r4(calc_cnt + 2) - r2(calc_cnt - 2) - r2(calc_cnt - 1) - r2(calc_cnt) - r2(calc_cnt + 1) - r2(calc_cnt + 2)); I know that a 13 bit wide result is ok for the numbers that I have, so i defined h_tmp as a signed (12 downto 0). Now, after synthesis I have the following warning Width mismatch. <h_tmp> has a width of

问题 The following VHDL is to be used to test bench. I keep getting an error on the first wait statement during analysis : "wait statement must contain condition clause with UNTIL keyword" I have several working test benches written this way. I can't seem to find what the error might be. `library IEEE; USE IEEE.std_logic_1164.all; entity case_ex_TB is end; architecture simple_test of case_ex_TB is --- DUT Component Declaration --- component case_ex port( clk, rstN: IN std_logic; color: OUT std