VHDL Selection machine error in port map

问题

I get this error:

# Error: COMP96_0100: data_reg.vhd : (156, 35): Actual parameter type in port map does not match the port formal type "Allin".
# Error: COMP96_0100: data_reg.vhd : (158, 1): Actual parameter type in port map does not match the port formal type "Fout".
# Error: COMP96_0100: data_reg.vhd : (162, 1): Actual parameter type in port map does not match the port formal type "D".
# Error: COMP96_0100: data_reg.vhd : (163, 1): Actual parameter type in port map does not match the port formal type "Q". 

I need some help, please.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ticket1 is
    port (
        A, B : in std_logic_vector(7 downto 0);
        Clock: in std_logic;
        O: out std_logic_vector(7 downto 0));
end entity;

architecture Ticketmachine of ticket1 is  

component ticket_selection 
    port(
        Allin:in bit_vector(3 downto 0);
        Clk: in std_logic;
        Fout: out bit_vector(7 downto 0));  
end component ticket_selection;

component  reg is  
    port(
        C: in std_logic;  
        D: in bit_vector(7 downto 0);
        Q : out bit_vector(7 downto 0));  
end component reg;        

component  Money is
    port (
        Ai,Bi : in std_logic_vector(7 downto 0);
        Fo: out std_logic_vector(7 downto 0));
end component money;

    signal s1,s2: std_logic_vector(7 downto 0);

begin 
    Option: ticket_selection
        port map(
            Allin=>A,
            Clk=>Clock,    
            Fout=>s1);

    Cash: reg
        port map(
            C=>Clock,
            D=>B,
            Q=>s2);

    Pros: Money
        port map(
            Ai=>s1,
            Bi=>s2,
            Fo=>O);
 end architecture;

回答1:

You should read carefully some VHDL guide for beginners. I can't recommend any (maybe someone could?), so I'll go straight to your mistakes here:

1. Never use std_logic_unsigned, std_logic_unsigned, and std_logic_arith. This libraries are not part of standard, and can be replaced with numeric_std.
2. Don't use bit or bit_vector type. Use std_logic, and std_logic_vector instead.
3. When you associate one vector to other, they must have equal type and length, as user1155120 and Brian Drummond wrote in comment. In particular, you can't assign std_logic_vector(7 downto 0) to bit_vector(3 downto 0).

There are probably more things done wrong here, but your question is not complete - you didn't provide any explanation what it should do, no full code, and no testbench.

来源：https://stackoverflow.com/questions/43956607/vhdl-selection-machine-error-in-port-map