Binary serial adder - VHDL

问题

I'm trying to design a 32bit binary serial adder in VHDL, using a structural description. The adder should make use of a full adder and a d-latch. The way I see it is:

Full adder:

architecture Behavioral of FullAdder is
begin

s <= (x xor y) xor cin;
cout <= (x and y) or (y and cin) or (x and cin);
end Behavioral;

D-Latch:

architecture Behavioral of dLatch is
begin
state: process(clk)
begin
    if(clk'event and clk = '1') then
        q <= d;
    end if;
end process;
end Behavioral;

Serial adder:

add: process ( clk )
    variable count : integer range 0 to 31;
        variable aux : STD_LOGIC;
        variable aux2 : STD_LOGIC;
    begin
        if(clk'event and clk = '1') then
        fa: FullAdder port map(x(count), y(count), aux, s(count), aux2);
                    dl: dLatch port map(clock, aux2, aux);
        count := count + 1; 
    end if;
     end process;

However, it doesn't seem to work. Also, what would be the simplest way to pipeline the serial adder?

回答1:

"It doesn't seem to work" is pretty general, but one problem I see is that you are trying to instantiate the component fa: FullAdder within a process. Think about what component instantiation means in hardware, and you will realize that it makes no sense to instantiate the module on the rising_edge of clk...

Move the instantiation out of the process, and it should at least remove the syntax error you should be seeing ("Illegal sequential statement." in ModelSim).

回答2:

For pipelining the serial adder, the best way is to connect the adders and d flip-flops one after the other. So, you would have the cout of the first adder be the input of a flip-flop. The output of that flip-flop will be the cin of the next adder and so on. Be careful though, because you will also have to pipeline the s of each adder, as well as each bit of the input, by essentially putting several d flip-flops in a row to copy them through the various pipeline stages.

来源：https://stackoverflow.com/questions/16931436/binary-serial-adder-vhdl

标签

vhdl