问题
Using Lattice Diamond 3.6.0.83.4 MachX03 starter kit
After a lot of struggling I figured out why many of my inputs were unconnected. It came down to some bad assignments in a debouncer module.
After I cleaned up the debouncer, everything worked fine, except for a handful of inputs. For some reason, these inputs refuse to connect to anything. I can't find much in the code because it's a lot of copy-pasting all over the place. I've exhaustively reviewed what I've done so it makes no sense to me why most of the code works, and 7 odd inputs refuse to connect.
library IEEE;
use IEEE.numeric_bit.all;
USE ieee.std_logic_1164.ALL;
Entity hostlogic IS
PORT(CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
STOP : IN STD_LOGIC;
EMGC : IN STD_LOGIC;
READY : IN STD_LOGIC;
XENABLE : IN STD_LOGIC;
XSIN, XDIN, XHIN, XLIN,
YSIN, YDIN, YHIN, YLIN,
ZSIN, ZDIN, ZHIN, ZLIN,
ASIN, ADIN, AHIN, ALIN,
BSIN, BDIN, BHIN, BLIN,
CSIN, CDIN, CHIN, CLIN,
errIN : IN STD_LOGIC;
XSOUT, XDOUT,
YSOUT, YDOUT,
ZSOUT, ZDOUT,
ASOUT, ADOUT,
BSOUT, BDOUT,
CSOUT, CDOUT,
errOUT: OUT STD_LOGIC;
PERIPHERALSIN: IN STD_LOGIC_VECTOR(15 DOWNTO 0); --FROM DEVICES TO SBC
PERIPHERALSOUT: OUT STD_lOGIC_VECTOR(15 DOWNTO 0); --FROM DEVICES TO SBC DEBOUNCED
PERIPH_DRIV_IN: IN STD_LOGIC_VECTOR(15 DOWNTO 0); --FROM SBC TO DEVICE
PERIPH_DRIV_OUT: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
); --FROM SBC TO DEVICE DEBOUNCED
END hostlogic;
ARCHITECTURE hostproc OF hostlogic IS
--SIGNAL LIST
--INTERNAL DEBOUNCED, OVR ENABLES, LIMIT ENABLES, COPY OF INPUTS FOR WIRES
signal ID_XS, ID_XD, XEN, XLIMS, ID_XLIN, ID_XHIN, I_XSIN, I_XDIN, I_XHIN, I_XLIN: std_logic;
signal ID_YS, ID_YD, YEN, YLIMS, ID_YLIN, ID_YHIN, I_YSIN, I_YDIN, I_YHIN, I_YLIN: std_logic;
signal ID_ZS, ID_ZD, ZEN, ZLIMS, ID_ZLIN, ID_ZHIN, I_ZSIN, I_ZDIN, I_ZHIN, I_ZLIN: std_logic;
signal ID_AS, ID_AD, AEN, ALIMS, ID_ALIN, ID_AHIN, I_ASIN, I_ADIN, I_AHIN, I_ALIN: std_logic;
signal ID_BS, ID_BD, BEN, BLIMS, ID_BLIN, ID_BHIN, I_BSIN, I_BDIN, I_BHIN, I_BLIN: std_logic;
signal ID_CS, ID_CD, CEN, CLIMS, ID_CLIN, ID_CHIN, I_CSIN, I_CDIN, I_CHIN, I_CLIN: std_logic;
SIGNAL I_RESET, I_STOP, I_EMGC, I_ERR, I_READY, ERR_MERGED, I_XENABLE: STD_LOGIC;
SIGNAL ID_RESET, ID_STOP, ID_EMGC, ID_ERR, ID_READY, ID_XENABLE: STD_LOGIC;
SIGNAL TESTER: STD_LOGIC;
signal STATE: integer;
SIGNAL IPERIPHERALS: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL IDRIVERS: STD_LOGIC_VECTOR(15 DOWNTO 0);
--COMPONENT LIST
COMPONENT stepper
PORT(
CLK : IN std_logic;
OVR : IN std_logic;
RESET: IN std_logic;
AXIAL: IN std_logic;
RADIAL: IN std_logic;
ERR: IN std_logic;
STOP: IN std_logic;
HLIM: IN std_logic;
stepin : IN std_logic;
dirin : IN std_logic;
dirout : OUT std_logic;
stepout: OUT std_logic
);
END COMPONENT;
COMPONENT DEBOUNCER
PORT(
CLK : IN std_logic;
DIN : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
begin
--LIMIT SWITCH ENABLES
XLIMS <= '1' ; --if high, limit enabled. If low, limit disabled.
YLIMS <= '1' ;
ZLIMS <= '1' ;
ALIMS <= '1' ;
BLIMS <= '1' ;
CLIMS <= '1' ;
--COPY INPUTS TO INTERNAL WIRES
--UNASSIGNED INPUTS WILL CAUSE ERROR IN SYSTEM
I_READY <= READY;
I_RESET <= RESET;
I_STOP <= STOP;
I_EMGC <= EMGC;
I_XENABLE <= XENABLE;
I_ERR <= ERRIN;
I_XSIN <= XSIN;
I_XDIN <= XDIN;
I_XHIN <= XHIN;
I_XLIN <= XLIN;
I_YSIN <= YSIN;
I_YDIN <= YDIN;
I_YHIN <= YHIN;
I_YLIN <= YLIN;
I_ZSIN <= ZSIN;
I_ZDIN <= ZDIN;
I_ZHIN <= ZHIN;
I_ZLIN <= ZLIN;
I_ASIN <= ASIN;
I_ADIN <= ADIN;
I_AHIN <= AHIN;
I_ALIN <= ALIN;
I_BSIN <= BSIN;
I_BDIN <= BDIN;
I_BHIN <= BHIN;
I_BLIN <= BLIN;
I_CSIN <= CSIN;
I_CDIN <= CDIN;
I_CHIN <= CHIN;
I_CLIN <= CLIN;
--SIGNAL OVERRIDE ENABLE SETTINGS
XEN <= '0'; --should be low to prevent damage to tool
YEN <= '0'; --should be low to prevent damage to tool
ZEN <= '1'; --should be high to move tool away from working surface
AEN <= '0'; --should be high for lave, low for plane, default is low
BEN <= '0'; --should be high for lave, low for plane, default is low
CEN <= '0'; --should be high for lave, low for plane, default is low
--COMPONENT INSTANTIATION
--STEPPERS
--XAXIS
XAXIS : stepper
PORT MAP(
CLK => CLK,
OVR => XEN,
RESET => RESET,
AXIAL => '1',
RADIAL => '0',
ERR => ERR_MERGED,
STOP => ID_STOP,
HLIM => ID_XHIN,
stepin => ID_XS,
dirin => ID_XD,
dirout => XDOUT,
stepout => XSOUT
);
--YAXIS
YAXIS: stepper
PORT MAP(
CLK => CLK,
OVR => YEN,
RESET => RESET,
AXIAL => '1',
RADIAL => '0',
ERR => ERR_MERGED,
STOP => ID_STOP,
HLIM => ID_YHIN,
stepin => ID_YS,
dirin => ID_YD,
dirout => YDOUT,
stepout => YSOUT
);
--ZAXIS
ZAXIS: stepper
PORT MAP(
CLK => CLK,
OVR => ZEN,
RESET => RESET,
AXIAL => '1',
RADIAL => '0',
ERR => ERR_MERGED,
STOP => ID_STOP,
HLIM => ID_ZHIN,
stepin => ID_ZS,
dirin => ID_ZD,
dirout => ZDOUT,
stepout => ZSOUT
);
--AAXIS
AAXIS: stepper
PORT MAP(
CLK => CLK,
OVR => AEN,
RESET => RESET,
AXIAL => '1',
RADIAL => '0',
ERR => ERR_MERGED,
STOP => ID_STOP,
HLIM => ID_AHIN,
stepin => ID_AS,
dirin => ID_AD,
dirout => ADOUT,
stepout => ASOUT
);
--BAXIS
BAXIS: stepper
PORT MAP(
CLK => CLK,
OVR => BEN,
RESET => RESET,
AXIAL => '1',
RADIAL => '0',
ERR => ERR_MERGED,
STOP => ID_STOP,
HLIM => ID_BHIN,
stepin => ID_BS,
dirin => ID_BD,
dirout => BDOUT,
stepout => BSOUT
);
--CAXIS
CAXIS: stepper
PORT MAP(
CLK => CLK,
OVR => CEN,
RESET => RESET,
AXIAL => '1',
RADIAL => '0',
ERR => ERR_MERGED,
STOP => ID_STOP,
HLIM => ID_CHIN,
stepin => ID_CS,
dirin => ID_CD,
dirout => CDOUT,
stepout => CSOUT
);
statemachine: process(CLK)
begin
case STATE is
--RESET/READY STATE
when 0 => --RESET/READY STATE
if ID_RESET = '1' then --RESET MUST STAY HIGH UNTIL MACHINE HAS FOUND ITS POSITION
STATE <= 0; --IF RESET HIGH, STAY IN RESET
elsif ID_RESET = '0' then
STATE <= 1; --IF RESET LOW, GO TO NORMAL OPERATION
end if;
--NORMAL OPERATION
when 1 => --NORMAL OPERATION
if ID_STOP = '0' then --IF ERROR THEN GO TO STOP STATE
STATE <= 2;
elsif ID_RESET <= '1' then --SINGAL FROME SBC, TRUE IS TRUE FALSE IS FALSE
STATE <= 0; --IF RESET SIGNAL GO TO RESET STATE
end if;
--STOP PROCEDURE
when 2 => --STOP PROCEDURE
if ID_RESET = '1' then --SIGNAL FROM SBC, TRUE IS TRUE, FALSE IS FALSE
STATE <= 0; --IF RESET HIGH, GO TO RESET AND IGNORE STOP
end if;
--CATCHALL STATE
when others => --CATCHALL REBOOT STATE
if ID_RESET = '1' then
STATE <= 0;
end if;
end case;
end process;
--DEBOUNCERS
--LIMITS
LIMITERS: DEBOUNCER
PORT MAP(
CLK => CLK,
DIN(0) => I_XHIN, --limit
DIN(1) => I_XLIN, --limit
DIN(2) => I_YHIN, --limit
DIN(3) => I_YLIN, --limit
DIN(4) => I_ZHIN, --limit
DIN(5) => I_ZLIN, --limit
DIN(6) => I_AHIN, --limit
DIN(7) => I_ALIN, --limit
DIN(8) => I_BHIN, --limit
DIN(9) => I_BLIN, --limit
DIN(10) => I_CHIN, --limit
DIN(11) => I_CLIN, --limit
DIN(12) => I_XDIN, --STEPPER DIRECTIOON
DIN(13) => I_YDIN, --STEPPER DIRECTIOON
DIN(14) => I_ZDIN, --STEPPER DIRECTIOON
DIN(15) => open,
DOUT(0) => ID_XHIN, --limit, internal
DOUT(1) => ID_XLIN, --limit, internal
DOUT(2) => ID_YHIN, --limit, internal
DOUT(3) => ID_YLIN, --limit, internal
DOUT(4) => ID_ZHIN, --limit, internal
DOUT(5) => ID_ZLIN, --limit, internal
DOUT(6) => ID_AHIN, --limit, internal
DOUT(7) => ID_ALIN, --limit, internal
DOUT(8) => ID_BHIN, --limit, internal
DOUT(9) => ID_BLIN, --limit, internal
DOUT(10) => ID_CHIN, --limit, internal
DOUT(11) => ID_CLIN, --limit, internal
DOUT(12) => ID_XD, --STEPPER DIRECTIOON, internal
DOUT(13) => ID_YD, --STEPPER DIRECTIOON, internal
DOUT(14) => ID_ZD, --STEPPER DIRECTIOON, internal
DOUT(15) => OPEN);
--DEBOUNCERS
--LIMITS
CONTROLS: DEBOUNCER
PORT MAP(
CLK => CLK,
DIN(0) => I_RESET, --From SBC
DIN(1) => I_STOP, --From SBC
DIN(2) => I_EMGC, --From Pushbutton
DIN(3) => I_READY, --From SBC
DIN(4) => I_XENABLE, --from SBC
DIN(5) => I_ERR, --from Peripherals
DIN(6) => I_XSIN, --STEPPER STEP INSTRUCTION
DIN(7) => I_YSIN, --STEPPER STEP INSTRUCTION
DIN(8) => I_ZSIN, --STEPPER STEP INSTRUCTION
DIN(9) => I_ASIN, --STEPPER STEP INSTRUCTION
DIN(10) => I_BSIN, --STEPPER STEP INSTRUCTION
DIN(11) => I_CSIN, --STEPPER STEP INSTRUCTION
DIN(12) => I_ADIN, --STEPPER DIRECTION
DIN(13) => I_BDIN, --STEPPER DIRECTION
DIN(14) => I_CDIN, --STEPPER DIRECTION
DIN(15) => OPEN,
DOUT(0) => ID_RESET, --internal reset signal
DOUT(1) => ID_STOP, --internal stop signal
DOUT(2) => ID_EMGC, --internal emergency signal
DOUT(3) => ID_READY, --internal ready signal
DOUT(4) => ID_XENABLE,--internal signal
DOUT(5) => ID_ERR, --internal signal
DOUT(6) => ID_XS, --stepper step instruction, internal
DOUT(7) => ID_YS, --stepper step instruction, internal
DOUT(8) => ID_ZS, --stepper step instruction, internal
DOUT(9) => ID_AS, --stepper step instruction, internal
DOUT(10) => ID_BS, --stepper step instruction, internal
DOUT(11) => ID_CS, --stepper step instruction, internal
DOUT(12) => ID_AD, --STEPPER DIRECTIOON, internal
DOUT(13) => ID_BD, --STEPPER DIRECTIOON, internal
DOUT(14) => ID_CD, --STEPPER DIRECTIOON, internal
DOUT(15) => OPEN);
--DEBOUNCERS
--PERIPHERAL END
PERIPH_IO: DEBOUNCER
PORT MAP(
CLK => CLK,
DIN => PERIPHERALSIN,
DOUT => IPERIPHERALS);
--DEBOUNCERS
--SBC END
PERIPH_DRIVER: DEBOUNCER
PORT MAP(
CLK => CLK,
DIN => PERIPH_DRIV_IN,
DOUT => IDRIVERS);
--INTERNAL SIGNALS TO OUTPUTS
PERIPHERALSOUT <= IPERIPHERALS;
PERIPH_DRIV_OUT <= IDRIVERS;
ERROUT <= ID_ERR;
--LIMIT ENABLER
--ERROR LOGIC
ERROR_LOGIC: PROCESS(CLK)
BEGIN
IF ID_RESET = '0' THEN
IF (ID_EMGC = '1' OR ID_STOP = '1') AND ID_RESET = '0' THEN --CHECK STOP TRIGGERS
ERR_MERGED <= '1' ;
ELSIF XEN = '0' AND ERR_MERGED = '0' THEN --CHECK X LIMITS IF NO OVERRIDE
IF ID_XHIN = '0' THEN
ERR_MERGED <= XLIMS; --PASS ERROR ON AXIS LIMITER CONDITION
ELSIF ID_XLIN = '0' THEN
ERR_MERGED <= XLIMS ;
END IF;
ELSIF YEN = '0' AND ERR_MERGED = '0' THEN --CHECK Y LIMITS IF NO OVERRIDE
IF ID_YHIN = '0' THEN
ERR_MERGED <= YLIMS ;
ELSIF ID_YLIN = '0' THEN --PASS ERROR ON AXIS LIMITER CONDITION
ERR_MERGED <= YLIMS ;
END IF;
ELSIF ZEN = '0' AND ERR_MERGED = '0' THEN --CHECK Z LIMITS IF NO OVERRIDE
IF ID_ZHIN = '0' THEN
ERR_MERGED <= ZLIMS ;
ELSIF ID_ZLIN = '0' THEN --PASS ERROR ON AXIS LIMITER CONDITION
ERR_MERGED <= ZLIMS ;
END IF;
ELSIF AEN = '0' AND ERR_MERGED = '0' THEN --CHECK A LIMITS IF NO OVERRIDE
IF ID_AHIN = '0' THEN
ERR_MERGED <= ALIMS ;
ELSIF ID_ALIN = '0' THEN --PASS ERROR ON AXIS LIMITER CONDITION
ERR_MERGED <= ALIMS ;
END IF;
ELSIF BEN = '0' AND ERR_MERGED = '0' THEN --CHECK B LIMITS IF NO OVERRIDE
IF ID_BHIN = '0' THEN
ERR_MERGED <= BLIMS ;
ELSIF ID_BLIN = '0' THEN --PASS ERROR ON AXIS LIMITER CONDITION
ERR_MERGED <= BLIMS ;
END IF;
ELSIF CEN = '0' AND ERR_MERGED = '0' THEN --CHECK C LIMITS IF NO OVERRIDE
IF ID_CHIN = '0' THEN
ERR_MERGED <= CLIMS ;
ELSIF ID_CLIN = '0' THEN --PASS ERROR ON AXIS LIMITER CONDITION
ERR_MERGED <= CLIMS ;
END IF;
END IF;
ELSIF ID_RESET = '1' THEN
ERR_MERGED <= '0';
END IF;
IF READY ='1' AND XENABLE = '1' THEN
TESTER <= '1';
ELSE
TESTER <= '0';
END IF;
END PROCESS;
end hostproc;
Once I try to assign pins, only the following ports remain unconnected:
READY, XENABLE, YHIN, YLIN, ZLIN, BHIN, BLIN.
There are two debouncer instances, so if the signals were going screwy in the same places, that'd explain it. However this is not the case as the signals appear to be disconnecting somewhere else. I'm completely at wits end on what to do. I've caught myself trying the same solutions again without luck, so it's time for me to step back for a bit before I resort to tearing my hair out.
来源：https://stackoverflow.com/questions/36008289/vhdl-arbitrarily-unconnected-components