hdl

问题 Signal driver_a is reassigned in the always block back to 0, but why is the always block not activating and assign value to driver_b ? always @(driver_a) begin driver_b = driver_a; driver_a = 0; end initial begin driver_a = 0; driver_b = 0; #2 driver_a = 8'h8; #2 driver_a = 8'hf; end In the waveform, I expect that after driver_a assigns its value to driver_b, then in the next line when driver_a gets assigned to 0, I'd expect the always block to reactivate and assign value 0 back to driver_b.

问题 I'm trying to generate an array of latches that are placed adjacent to each other using a Generate statement. I've been trying to use the Xilinx constraint "RLOC" to do this, but I haven't been successful. The code below won't successfully implement, but should illustrate what I'm trying to obtain. The issue with the code below is that "i" in the constraint call isn't being converted into a string, which is what the call is looking for. Does anyone have experience doing this? I'm using a

问题 When I go to simulate my top-level module in Xilinx Vivado 2016.4, I receive the peculiar error: ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [<...>/header.vh] I am using the built-in Vivado Simulator with Verilog 2001 specified. My header.vh looks like the following: `ifndef _header_vh_ `define _header_vh_ function integer clog2; input integer value; begin value = value - 1; for (clog2 = 0; value > 0; clog2 = clog2 + 1) value = value >> 1; end endfunction

问题 When I go to simulate my top-level module in Xilinx Vivado 2016.4, I receive the peculiar error: ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [<...>/header.vh] I am using the built-in Vivado Simulator with Verilog 2001 specified. My header.vh looks like the following: `ifndef _header_vh_ `define _header_vh_ function integer clog2; input integer value; begin value = value - 1; for (clog2 = 0; value > 0; clog2 = clog2 + 1) value = value >> 1; end endfunction

问题 I am an undergrad doing my second year. I am required to simulate Verilog programs as part of my syllabus. But sadly my college uses Xilinx ISE and it isn't available for Mac. So please help me out with the best software and also some detailed steps on how to install and use them. Thanks in advance.:) :D 回答1: You could try Icarus Verilog, which is a free Verilog simulator. According to the instructions here you can install Icarus Verilog on Mac OS X. 来源： https://stackoverflow.com/questions

问题 this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four digit seven segment display on a BASYS2 board. I have checked to make sure that 0 enables the signal and that I have the ports mapped correctly. I believe the error is within my multiplexing logic since I am only able to display a single digit. I'm new to Verilog (am used to C) and would appreciate any suggestions. Thanks `timescale 1ns / 1ps module main (clock, AN0, AN1, AN2, AN3, CA, CB, CC,

问题 I am trying to write a BCD Adder in Verilog, but I am having trouble with one of the modules. Specifically, the adder that takes two BCD digits and adds them. So, the idea is if the sum of the two digits is less than or equal to nine, then it is correct. However, if it is greater, then an offset of 6 has to be added. Here is my Verilog code so far: module DIGITADD( input [3:0] IN_A, input [3:0] IN_B, input CIN, output reg COUT, output reg [3:0] SUM ); wire s2, c2; always @ ( * ) begin assign

问题 I need to read a small image (tif format) from PC to FPGA kit (ALTERA DE2-70) for processing, then write it back to PC. I have no idea how to do it in Verilog? Can it be done in C? if so, how can I combine my C/HDL code to work together? Thank you! 回答1: a few mounts ago i were having the same problem, but i wanted to send and receive a real time image. back then i was researching and the best (fast an chip) solution that i find was the XEM6001 of opalkelly. http://www.opalkelly.com/products

问题 How do you implement a hardware random number generator in an HDL (verilog)? What options need to be considered? This question is following the self-answer format. Addition answers and updates are encouraged. 回答1: As noted in Morgan's answer this will only produce a single random bit. The number of bits in the LFSR only set how many values you get before the sequence repeats. If you want an N bit random number you have to run the LFSR for N cycles. However, if you want a new number every

问题 would an always block with no sensitivity list infer a combinational logic, just the same as always_comb or always @(*) ? Eg code: always begin if (sig_a)begin @(posedge sig_b); // wait for a sig_b posedge event @(negedge sig_b); // then wait for a sig_b negedge event event_true=1; end if (event_true)begin @((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true yes =1; end else yes =0; end 回答1: Synthesis tools require a specific template coding style to