问题
I get the following error when compiling RISCV VERILOG HDL on Xilinx ISE:
It says "Unsupported System Function Call" in the following code at line 296 in module vscale_pipeline
295: ifndef SYNTHESIS
296: PC_WB <= $random;
回答1:
Some synthesis tools define the SYNTHESIS macro so that it is easier to skip non-synthesizable code in synthesis using
`ifdef SYNTHESIS
...
`endif
blocks, as is done in this code.
Xilinx XST does not define this macro by default, so you have to configure XST manually to define the macro during synthesis. See this Xilinx AR for details on how to do that.
回答2:
$random isn't synthesizable, so take it out
来源：https://stackoverflow.com/questions/36963597/riscv-verilog-hdl-code