问题
I have written a Verilog code, this code to describe a combinational module. I used a blocking assignment. in other parts, there is must use a nonblocking assignment. can I use a delay in the blocking assignment to be alternative to a nonblocking assignment... I don't want to mix these two assignments in one module
`timescale 1ns / 1ps
module buffer(datain1,datain2,datain3,datain4,
s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,
src_out1,src_out2,src_out3,
src_out4,src_out5,src_out6,
src_out7,src_out8,src_out9,
src_out10,src_out11,src_out12,
c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,
start,clk,load2ads,rb,
post_id1,post_id2,post_id3,post_id4,
post_r1,post_r2,post_r3,post_r4);
input [9:0] post_r1,post_r2,post_r3,post_r4;
input [5:0] post_id1,post_id2,post_id3,post_id4;
input [2:0] c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12;
input [87:0] datain1,datain2,datain3,datain4; // alu result
input [5:0] s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12; // task number from ads table
input start,clk;
output reg [87:0] src_out1,src_out2,src_out3, // all information from buffer to execution array
src_out4,src_out5,src_out6, // available sources heading from buff to array
src_out7,src_out8,src_out9,
src_out10,src_out11,src_out12;
output reg rb;
output reg load2ads;
reg [9:0]a,b;
reg [263:0] // register for temporary save of alu's results
t_ads1,t_ads2,t_ads3,
t_ads4,t_ads5,t_ads6,
t_ads7,t_ads8,t_ads9,
t_ads10,t_ads11,t_ads12;
reg [29:0] temp1,temp2,temp3,temp4;
reg [9:0] buff;
reg [263:0] buffer [0:63];
reg [5:0] address_in1,address_in2,address_in3,address_in4; // register for temporary save of alu's addresses
always@(start or datain1 or datain2 or datain3 or datain4
or s1 or s2 or s3 or s4 or s5 or s6 or s7 or s8 or s9 or s10 or s11 or s12
or c1 or c2 or c3 or c4 or c5 or c6 or c7 or c8 or c9 or c10 or c11 or c12)
begin
if(start)
begin
buffer[0]= 0;
buffer[1]=264'b000100001011111100000000000100000000000000100001000000000000000000000000000000001000000000010000101111110000000000010000000000000010001100000000000000000000000000000000100000000001000010111111000000000001000000000000001001010000000000000000000000000000000010000000;
buffer[2]=264'b000100001000000100000000001000000000000010100001000000000000000000000000000000000100000000010000100000010000000000100000000001001001001100000000000000000000000000000000010000000001000010000001000000000010000000000100010101010000000000000000000000000000000001000000;
buffer[3]=264'b000100001000001000000000001100000000000000100001000000000000000000000000000000000100000000010000100000100000000000110000000000000010001100000000000000000000000000000000010000000001000010000010000000000011000000000000001001010000000000000000000000000000000001000000;
buffer[4]=264'b000100001000001100000000010000000000000000000001000000000000000000000000000000001000000000010000100000110000000001000000000000000000001100000000000000000000000000000000100000000001000010000011000000000100000000000000000001010000000000000000000000000000000010000000;
buffer[63]=264'b00000000000000000000011111100000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
end
////////////////////////////////////////////////////////////
rb=0;
/*address_in1=datain1[65:60];
address_in2=datain2[65:60];
address_in3=datain3[65:60];
address_in4=datain4[65:60];
*/
buffer [datain1[65:60]][263:176]=datain1;
buffer [datain2[65:60]][263:176]=datain2;
buffer [datain3[65:60]][263:176]=datain3;
buffer [datain4[65:60]][263:176]=datain4;
// insert alu result into buffer and shift the data into the next ctr
if(s1 !=0)
begin
t_ads1 =buffer[s1];
if(c1==0) begin src_out1=t_ads1[263:176];src_out1[43:41]=0; end
else if(c1==1) begin src_out1=t_ads1[175:88]; src_out1[43:41]=1; end
else if(c1==2) begin src_out1=t_ads1[87:0]; src_out1[43:41]=2; end
else src_out1=0;
end
else src_out1=0;
if(s2 !=0)
begin
t_ads2 =buffer[s2];
if(c2==0) begin src_out2=t_ads2[263:176];src_out2[43:41]=0;end
else if(c2==1) begin src_out2=t_ads2[175:88]; src_out2[43:41]=1;end
else if(c2==2) begin src_out2=t_ads2[87:0]; src_out2[43:41]=2;end
else src_out2=0;
end
else src_out2=0;
if(s3 !=0)
begin
t_ads3 =buffer[s3];
if(c3==0) begin src_out3=t_ads3[263:176];src_out3[43:41]=0; end
else if(c3==1) begin src_out3=t_ads3[175:88];src_out3[43:41]=1; end
else if(c3==2) begin src_out3=t_ads3[87:0];src_out3[43:41]=2; end
else src_out3=0;
end
else src_out3=0;
////////////////////////////////////////////////////////////////
if(s4 !=0)
begin
t_ads4 =buffer[s4];
if(c4==0) begin src_out4=t_ads4[263:176]; src_out4[43:41]=0; end
else if(c4==1) begin src_out4=t_ads4[175:88]; src_out4[43:41]=1; end
else if(c4==2) begin src_out4=t_ads4[87:0];src_out4[43:41]=2; end
else src_out4=0;
end
else src_out4=0;
if(s5 !=0)
begin
t_ads5 =buffer[s5];
if(c5==0) begin src_out5=t_ads5[263:176]; src_out5[43:41]=0; end
else if(c5==1) begin src_out5=t_ads5[175:88]; src_out5[43:41]=1; end
else if(c5==2) begin src_out5=t_ads5[87:0]; src_out5[43:41]=2; end
else src_out5=0;
end
else src_out5=0;
if(s6 !=0)
begin
t_ads6 =buffer[s6];
if(c6==0) begin src_out6=t_ads6[263:176]; src_out6[43:41]=0; end
else if(c6==1) begin src_out6=t_ads6[175:88]; src_out6[43:41]=1; end
else if(c6==2) begin src_out6=t_ads6[87:0]; src_out6[43:41]=2; end
else src_out6=0;
end
else src_out6=0;
///////////////////////////////////////////////////////////////////////////
if(s7 !=0)
begin
t_ads7 =buffer[s7];
if(c7==0) begin src_out7=t_ads7[263:176]; src_out7[43:41]=0; end
else if(c7==1) begin src_out7=t_ads7[175:88]; src_out7[43:41]=1; end
else if(c7==2) begin src_out7=t_ads7[87:0]; src_out7[43:41]=2; end
else src_out7=0;
end
else src_out7=0;
if(s8 !=0)
begin
t_ads8 =buffer[s8];
if(c8==0) begin src_out8=t_ads8[263:176]; src_out8[43:41]=0; end
else if(c8==1) begin src_out8=t_ads8[175:88]; src_out8[43:41]=1; end
else if(c8==2)begin src_out8=t_ads8[87:0];src_out8[43:41]=2; end
else src_out8=0;
end
else src_out8=0;
if(s9 !=0)
begin
t_ads9 =buffer[s9];
if(c9==0)begin src_out9=t_ads9[263:176]; src_out9[43:41]=0; end
else if(c9==1)begin src_out9=t_ads9[175:88]; src_out9[43:41]=1; end
else if(c9==2)begin src_out9=t_ads9[87:0]; src_out9[43:41]=2; end
else src_out9=0;
end
else src_out9=0;
/////////////////////////////////////////////////////////////////////
if(s10 !=0)
begin
t_ads10 =buffer[s10];
if(c10==0)begin src_out10=t_ads10[263:176]; src_out10[43:41]=0; end
else if(c10==1)begin src_out10=t_ads10[175:88];src_out10[43:41]=1; end
else if(c10==2)begin src_out10=t_ads10[87:0];src_out10[43:41]=2; end
else src_out10=0;
end
else src_out10=0;
if(s11 !=0)
begin
t_ads11 =buffer[s11];
if(c11==0)begin src_out11=t_ads11[263:176];src_out11[43:41]=0; end
else if(c11==1)begin src_out11=t_ads11[175:88];src_out11[43:41]=1; end
else if(c11==2)begin src_out11=t_ads11[87:0];src_out11[43:41]=2; end
else src_out11=0;
end
else src_out11=0;
if(s12 !=0)
begin
t_ads12 =buffer[s12];
if(c12==0)begin src_out12=t_ads12[263:176];src_out12[43:41]=0; end
else if(c12==1)begin src_out12=t_ads12[175:88];src_out12[43:41]=1; end
else if(c12==2)begin src_out12=t_ads12[87:0];src_out12[43:41]=2; end
else src_out12=0;
end
else src_out12=0;
this part I want to use an equivalent alternative way
if((datain1[49]==1)||(datain2[49]==1)||(datain3[49]==1)||(datain4[49]==1))
begin
buffer[1][59:50] <=buffer[1][147:138];
buffer[1][147:138]<=buffer[1][235:226];
buffer[2][59:50] <=buffer[2][147:138];
buffer[2][147:138]<=buffer[2][235:226];
buffer[3][59:50] <=buffer[3][147:138];
buffer[3][147:138]<=buffer[3][235:226];
buffer[4][59:50] <=buffer[4][147:138];
buffer[4][147:138]<=buffer[4][235:226];
buffer[5][59:50] <=buffer[5][147:138];
buffer[5][147:138]<=buffer[5][235:226];
buffer[6][59:50] <=buffer[6][147:138];
buffer[6][147:138]<=buffer[6][235:226];
buffer[7][59:50] <=buffer[7][147:138];
buffer[7][147:138]<=buffer[7][235:226];
buffer[8][59:50] <=buffer[8][147:138];
buffer[8][147:138]<=buffer[8][235:226];
buffer[9][59:50] <=buffer[9][147:138];
buffer[9][147:138]<=buffer[9][235:226];
buffer[10][59:50] <=buffer[10][147:138];
buffer[10][147:138]<=buffer[10][235:226];
buffer[11][59:50] <=buffer[11][147:138];
buffer[11][147:138]<=buffer[11][235:226];
buffer[12][59:50] <=buffer[12][147:138];
buffer[12][147:138]<=buffer[12][235:226];
buffer[13][59:50] <=buffer[13][147:138];
buffer[13][147:138]<=buffer[13][235:226];
buffer[14][59:50] <=buffer[14][147:138];
buffer[14][147:138]<=buffer[14][235:226];
buffer[15][59:50] <=buffer[15][147:138];
buffer[15][147:138]<=buffer[15][235:226];
buffer[16][59:50] <=buffer[16][147:138];
buffer[16][147:138]<=buffer[16][235:226];
buffer[17][59:50] <=buffer[17][147:138];
buffer[17][147:138]<=buffer[17][235:226];
buffer[18][59:50] <=buffer[18][147:138];
buffer[18][147:138]<=buffer[18][235:226];
buffer[19][59:50] <=buffer[19][147:138];
buffer[19][147:138]<=buffer[19][235:226];
buffer[20][59:50] <=buffer[20][147:138];
buffer[20][147:138]<=buffer[20][235:226];
buffer[21][59:50] <=buffer[21][147:138];
buffer[21][147:138]<=buffer[21][235:226];
buffer[22][59:50] <=buffer[22][147:138];
buffer[22][147:138]<=buffer[22][235:226];
buffer[23][59:50] <=buffer[23][147:138];
buffer[23][147:138]<=buffer[23][235:226];
buffer[24][59:50] <=buffer[24][147:138];
buffer[24][147:138]<=buffer[24][235:226];
buffer[25][59:50] <=buffer[25][147:138];
buffer[25][147:138]<=buffer[25][235:226];
buffer[26][59:50] <=buffer[26][147:138];
buffer[26][147:138]<=buffer[26][235:226];
rb=1;
end
end
endmodule
回答1:
You should not use Nonblocking Assignments in Combinational logic ideally.
Hence in your design, there are serious issues regarding timings.
However, if you make your design synchronous, then you can avoid the usage of NBA with the use of Clocking Block in Systemverilog.
clocking cb @(posedge clk)
input a, b, c;
// Other Signals as per your requirement
endclocking
Now the inputs declared in the clocking block by default have #1step delay, which means that they will hold the value of preponed region of current timeslot or postponed region of previous timeslot (which both are equal).
Hence you can use those signals anywhere in your design and you can eliminate the usage of NBA.
However, one thing to note is that Clocking Blocks are not synthesizable.
Here is one working example :
module temp();
reg a, b, c;
reg clock;
initial
begin
$monitor("@%0t: a - %b, b - %b, c - %b", $time(), a, b, c);
clock = 1;
a = 1;
b = 0;
c = 1;
#100 $finish();
end
always #5 clock = ~clock;
clocking cb @(negedge clock);
input a, b, c;
endclocking
always @(posedge clock)
begin
a = cb.c;
b = cb.a;
c = cb.b;
end
endmodule
Please note that if you keep both clocking event and always block event same (like both posedge/negedge), then there can be a potential race condition between them and the value sampled as input from clocking block may be inaccurate.
来源：https://stackoverflow.com/questions/42391563/is-there-an-alternative-to-non-blocking-assignment-in-verilog