Verilog error: not a valid l-value
问题 I'm trying to test if a wire(s) is on or not to signify if there is an error/overflow in my alu code. Given this code: output reg[3:0]x; // line 149 output wire error; output wire overflow; always @* begin if(error || overflow) begin assign x = 4'b1111; // line 155 assign error = ~error; assign overflow = ~overflow; end else begin assign x = opcode; end end I get following error messages: uut is my instantiation unit in my testbench called main 回答1: The code in the example has several issues.