alu

I'm trying to combine several 1 bit ALUs into a 4 bit ALU. I am confused about how to actually do this in VHDL. Here is the code for the 1bit ALU that I am using: component alu1 -- define the 1 bit alu component port(a, b: std_logic_vector(1 downto 0); m: in std_logic_vector(1 downto 0); result: out std_logic_vector(1 downto 0)); end alu1; architecture behv1 of alu1 is begin process(a, b, m) begin case m is when "00" => result <= a + b; when "01" => result <= a + (not b) + 1; when "10" => result <= a and b; when "11" => result <= a or b; end case end process end behv1 I am assuming I define

Hello I am trying to create a 16-bit ALU from several 1-bit ALUs I created a package named basic_alu1 which contains a component of the 1-bit ALU.The code for this is: library ieee; use ieee.std_logic_1164.all; package basic_alu1 is component alu1 port (a, b: std_logic_vector(1 downto 0); m: in std_logic_vector(1 downto 0); result: out std_logic_vector(1 downto 0)); end component; end package basic_alu1; library ieee; use ieee.std_logic_1164.all; entity alu1 is port (a, b: std_logic_vector(1 downto 0); m: in std_logic_vector(1 downto 0); result: out std_logic_vector(1 downto 0)); end alu1;

How are bit shifts implemented at the hardware level when the number to shift by is unknown? I can't imagine that there would be a separate circuit for each number you can shift by (that would 64 shift circuits on a 64-bit machine), nor can I imagine that it would be a loop of shifts by one (that would take up to 64 shift cycles on a 64-bit machine). Is it some sort of compromise between the two or is there some clever trick? The circuit is called a " barrel shifter " - it's a load of multiplexers basically. It has a layer per address-bit-of-shift-required, so an 8-bit barrel shifter needs