VHDL indexed name issue

问题

i get this error in this code: ter.vhd(31): Cannot resolve indexed name (type ieee.std_logic_1164.STD_ULOGIC) as type std.STANDARD.BOOLEAN. any idea how to fix it? i sincerly don't get what's wrong, tried with a web search, but nothing. thanks in advance!

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY inverter IS
GENERIC(size: integer); 
PORT ( 
     a : IN std_ulogic_vector(size-1 DOWNTO 0);
     b : OUT std_ulogic_vector(size-1 DOWNTO 0);
     carry : OUT std_ulogic;
     mode : IN std_ulogic
   );
END ENTITY inverter;


ARCHITECTURE behavioral OF inverter IS
COMPONENT alu IS
GENERIC(size: integer); 
Port ( X : in  std_ulogic_VECTOR (size-1 downto 0);
       Y : in  std_ulogic_VECTOR (size-1 downto 0);
       SUM : out  std_ulogic_VECTOR (size-1 downto 0);
       CARRY : out std_ulogic);
end COMPONENT;

SIGNAL z, c : std_ulogic_VECTOR( size-1 downto 0);

BEGIN
start: process(a,mode)
begin
z <= (others => '0');

IF a(size-1) THEN
c <= not a; 
z(0) <=  '1';
ELSIF (mode = '1') THEN 
c <= not a; 
z(0) <=  '1';
ELSE
c <= a;
END IF;
end process;
alu1: alu 
generic map(size)
PORT MAP(x => c, y => z, sum => b, carry => carry);


END ARCHITECTURE behavioral;

来源：https://stackoverflow.com/questions/40960820/vhdl-indexed-name-issue