问题
In an answer, jww points out that 1's complement is still used in encoding vector instructions on intel architectures, and Ruslan clarifies that these instructions are being used more as auto-vectorization becomes common.
Is there an advantage of 1's complement that causes it to continue to be used in these instructions, or is it simply being used for historical reasons?
Quoting jww:
From Intel® 64 and IA-32 Architectures Software Developer’s Manual 2A, page 3-8:
3.1.1.8 Description Section
Each instruction is then described by number of information sections. The “Description” section describes the purpose of the instructions and required operands in more detail.
Summary of terms that may be used in the description section:
* Legacy SSE: Refers to SSE, SSE2, SSE3, SSSE3, SSE4, AESNI, PCLMULQDQ and any future instruction sets referencing XMM registers and encoded without a VEX prefix.
* VEX.vvvv. The VEX bitfield specifying a source or destination register (in 1’s complement form).
* rm_field: shorthand for the ModR/M r/m field and any REX.B
* reg_field: shorthand for the ModR/M reg field and any REX.R
回答1:
That article isn't talking about 1's complement being used for integer storage. Even VEX-encoded integer instructions are going to act on 2's compliment integers.
All that 1's compliment is saying there is that an encoded register ID in a VEX instruction needs to have the normal bits used to ID the register flipped. Some in that question speculated this was to prevent clashes with existing instructions which makes plenty of sense to me.
来源：https://stackoverflow.com/questions/45244228/why-is-1s-complement-still-used-for-encoding-vector-instructions