how to delay a signal for several cycles in vhdl

问题

How to delay signal for a given number of cycles in VHDL? Number of cycles is given as a generic.

Any other options instead of

process(CLK) is
begin
  if rising_edge(CLK) then
    a_q <= a;
    a_q_q <= a_q;
    a_q_q_q <= a_q_q;
    -- etc
  end if;
end process;

?

回答1:

Create an 1-d array (let's call it a_store) of the appropriate type of signal with the length of the array related to the number of cycles. This may mean you have to create a new type for the array unless there's already a vector type you can use: eg. std_logic_vector or integer_vector (the latter is standard only in VHDL-2008).

Then shuffle the array along each tick:

if rising_edge(clk) then
  a_store <= a_store(store'high-1 downto 0) & a;
  a_out <= a_store(a_store'high);
end if;

来源：https://stackoverflow.com/questions/7918133/how-to-delay-a-signal-for-several-cycles-in-vhdl