Read textfile in VHDL testbench

问题

I have a file source.txt, it looks like this:

00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
0065006500660067006700690069006A006B006C006E
00650065006600670067006700680069006A006C006D
00650065006600670067006600660068006A006B006D
006500650066006700670065006600670069006B006D
00650065006600670067006600670068006A006C006D
0065006500660067006700690069006A006B006C006E
*

After each line there is the hidden newline character '\n'. The asterix '*' is my visible end-of-file character.

How do I write a testbench in VHDL that does the following:

read file
store one line in a vector
write that vector in a new target.txt

回答1:

Using VHDL-2008, and showing the std_logic_vector underway, the code can be:

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity tb is
end entity;

architecture syn of tb is
begin
  process is
    variable line_v : line;
    file read_file : text;
    file write_file : text;
    variable slv_v : std_logic_vector(44 * 4 - 1 downto 0);
  begin
    file_open(read_file, "source.txt", read_mode);
    file_open(write_file, "target.txt", write_mode);
    while not endfile(read_file) loop
      readline(read_file, line_v);
      hread(line_v, slv_v);
      report "slv_v: " & to_hstring(slv_v);
      hwrite(line_v, slv_v);
      writeline(write_file, line_v);
    end loop;
    file_close(read_file);
    file_close(write_file);
    wait;
  end process;
end architecture;

来源：https://stackoverflow.com/questions/37863515/read-textfile-in-vhdl-testbench

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vhdl