Signal temp2 cannot be synthesized, bad synchronous description

问题

entity timer is
    Port ( click : in  STD_LOGIC;
           clear : out  STD_LOGIC;
           t_unlock : out  STD_LOGIC);
end timer;

architecture Behavioral of timer is
    signal temp2 : integer range 0 to 20 := 0;
begin
    process
    begin
        if rising_edge(click) then
            temp2<=0;
            clear<='0';
            t_unlock<='0';
        else
            temp2<=temp2+1 after 15 ns;
        end if;
        if temp2=6 then
            clear<='1';
        elsif temp2=20 then
            t_unlock<='1';
        end if;
    end process;
end Behavioral;

I have writted this code.And the complier say:

Signal temp2 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

I have searched on stackoverflow.They say The error 'bad synchronous description' usually means that you have described a register (clocked element) that does not exist in the hardware.But I don't know how to solve my problem.

回答1:

The VHDL has to follow some synthesis tool specific coding guidelines, for the tool to be able to translate the VHDL code into the FPGA implementation. For implementation to a flip-flop with asynchronous reset, the style can be:

process (clk, rst) is
begin
  -- Clock
  if rising_edge(clk) then
    ... -- Update at clock
  end if;
  -- Asynchronous reset
  if rst = '1' then
    ... -- Update at reset
  end if;
end process;

In the case of your code it looks like you are not using the asynchronous reset, thus the template may be reduced to:

process (clk) is
begin
  if rising_edge(clk) then
    ... -- Update at clock
  end if;
end process;

The exercise is now for you to fit your code into that template, and unfortunately it is pretty hard to determine the exact intention based on the provided code.

回答2:

Your code seems to mix concepts of HDL and "software" languages. I'm not sure what it's supposed to do, but I would refactor it into the code below

architecture Behavioral of timer is
    constant COUNTER_VALUE_TO_REACH_15ns : integer := <some value>;

    signal temp2   : integer range 0 to 20 := 0;
    signal divider : std_logic_vector(7 downto 0) := (others => '0');
begin
    process
    begin
        -- Everything happens when the clock ticks, except for reset
        if rising_edge(click) then
            temp2    <= 0;
            clear    <= '0';
            t_unlock <= '0';

            -- Count how many cycles until we need to increment temp2
            if divider = COUNTER_VALUE_TO_REACH_15ns then
                temp2   <= temp2 + 1;
                divider <= (others => '0'); -- Reset the counter when we reach the required amount of time
            else
                divider <= divider + 1;
            end if;

            if temp2 = 6 then
                clear <= '1';
            elsif temp2 = 20 then
                t_unlock <= '1';
            end if;

        else
        end if;
    end process;
end Behavioral;

来源：https://stackoverflow.com/questions/34067622/signal-temp2-cannot-be-synthesized-bad-synchronous-description

标签

vhdl