Call task from another Verilog module
问题 I'm trying to learn Verilog and I have a Verilog module and what I wish to do is then call another file and run that from within my current module. So I have my module like: module maths(); //register etc details initial begin `include "add.v" end endmodule and my add.v file that is being called from the maths module is like: task add; A = $random; B = $random; C = A + B; $display("Answer: %d", C); endtask But I am receiving the errors from the task file near "task": syntax error, unexpected