Call task from another Verilog module

问题

I'm trying to learn Verilog and I have a Verilog module and what I wish to do is then call another file and run that from within my current module.

So I have my module like:

module maths();
//register etc details
initial begin

`include "add.v"

end
endmodule

and my add.v file that is being called from the maths module is like:

task add;
    A = $random;
    B = $random;
    C = A + B;
    $display("Answer: %d", C);
endtask

But I am receiving the errors from the task file near "task": syntax error, unexpected "task" and near "endtask": syntax error, unexpected "endtask".

I read the answer at How to call tasks from a separate module in Verilog? but the answer given there about needing to call the task from within an initial or always block hasn't helped because it is within an initial block in the module.

Where am I going wrong with this?

回答1:

Like Serge said, always include your files in the beginning of the file, right before the module statement.

`include "add.v"

module maths();
//register etc details
initial begin
    add;
end
endmodule

As for the problem, you are missing begin-end statements in the add task. Tasks always need these two statements to wrap your task code.

So, this should work:

reg A, B, C;

task add;
begin
    A = $random;
    B = $random;
    C = A + B;
    $display("Answer: %d", C);
end
endtask

Don't forget about A, B, C declarations :) !

来源：https://stackoverflow.com/questions/46837856/call-task-from-another-verilog-module