synthesis

this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four digit seven segment display on a BASYS2 board. I have checked to make sure that 0 enables the signal and that I have the ports mapped correctly. I believe the error is within my multiplexing logic since I am only able to display a single digit. I'm new to Verilog (am used to C) and would appreciate any suggestions. Thanks `timescale 1ns / 1ps module main (clock, AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE, CF, CG, CDP); //USED FOR SEVEN SEG input clock; output AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE,

Flip-Flops(,Registers ...) are usually triggered by a rising or falling edge. But mostly in code you see an if-clause which uses the rising edge triggering. In fact i never saw a code with falling edge. Why is that? Is it because naturally the programmers use rising edge, because they are used to, or is it because of some physical/analog law/fact, where the rising edge programming is faster/simpler/energy-efficient/... ? As zennehoy says, it's convention - but one going back to when logic was done in discrete chips with a few gates or flipflops within them. Those packages of flipflops were

my problem is that when I implement my design using Xilinx ISE 14.7 + XPS I often obtain a very different number of analyzed paths in the static timing analysis, also having very few differences in the .vhd files. In particular, the only file that I change (or that I think to change...) is something like: entity my_entity is( ... data_in : in std_logic_vector(N*B-1 downto 0); ... ); end entity my_entity; architecture bhv of my_entity is signal data : std_logic_vector(B-1 downto 0); signal idx_vect : std_logic_vector(log2(N)-1 downto 0); signal idx : integer range 0 to N-1; ... begin process

I've gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I've taken this habit over to coding for circuits which should be synthesizable. XST and others refuse to synthesize code (without additional modification to synthesis parameters) such as: while (num < test_number) begin . . . num = num+1; end This is bad coding style because to the synthesizer test_num is an int with value 2^32! or it sees it as unbounded parameter. Either way, its a bad coding habit. But I'm so used to doing this in C and testbenches.