Is $readmem synthesizable in Verilog?
问题 I am trying to implement a microcontroller on an FPGA, and I need to give it a ROM for its program. If I use $readmemb, will that be correctly synthesized to a ROM? If not, what is the standard way to do this? 回答1: I would amend George's answer to say that it depends on the synthesis tool whether or not $readmemb is synthesizable. Altera's Recommended HDL Coding Styles guide includes example 10-31 (page 10-38), which demonstrates a ROM inferred from $readmemb (reproduced below): module dual