synthesis

问题 I am trying to copy a 2d array into another like so: reg [11:0] input_matrix [0:array_width - 1] [0:array_height - 1]; reg [11:0] output_matrix [0:array_width - 1] [0:array_height - 1]; always @(posedge clk) begin if(<some condition>) output_matrix <= input_matrix; end So, we have two 2D arrays of 12-bit values. I'd like to copy one into the other. This doesn't seem to be possible. Does anyone know the correct way to do this? Or, if not, explain why it's not possible? I can't see any reason

问题 I am creating a package that has multiple definitions similar to the following -- Control Register Address Type Declaration SUBTYPE ctrl_reg_addr_type IS std_logic_vector( ADDR_BITS-1 DOWNTO 0 ); -- Control Register Data Type Declaration SUBTYPE ctrl_reg_data_type IS std_logic_vector( DATA_BITS-1 DOWNTO 0 ); -- Control Register Type Declaration SUBTYPE ctrl_reg_word_type IS std_logic_vector( CTRL_BITS-1 DOWNTO 0 ); -- Left/Right Line-In Control Type Declarations CONSTANT LINE_IN_VOL_BITS :

问题 I wrote some cross platform VHDL libraries for Xilinx XST, iSim, Altera Quartus II, Mentor Graphics QuestaSim and GHDL. Now I wanted to port my ISE 14.7 project, which uses these libraries to Vivado 2014.4, but one library seems to have fatal problems. My library physical defines several new user defined physical types like: FREQUENCY and BAUD ; conversion functions and report functions. One main use case is the calculation of delay or counter cycles for a given delay and system frequency. So

问题 I've been working on a packet sorting pipeline in VHDL using Xilinx ISE 14.2. In order to make the structure generic I wrote a few algorithms in a package that will determine how to connect sorting nodes. Interestingly when I design a test bench around the functions the results are correct. When I simulate my design in the project using a combination of generates and functions the hardware is wired correctly. (used 'assert false report " & integer'image(layer);' to validate in simulation)

问题 After synthesizing a processor code using Synopsis DC tool Now I want to initialize 2 rams included in 2 components in this design using .mem files how do I achieve that using the netlist file I have - the output of synthesizing - because I want to test if synthesizing was done right by testing the same code again on processor It was easier without before synthesizing just by loading .mem files into those rams and then testing it Any help 回答1: Don't bother loading .mem files; just initialise

问题 I am trying to successively subtract a particular number to get the last digit of the number (without division). For example when q=54, we get q=4 after the loop. Same goes for q=205, output is q=5. if(q>10) while(q>10) begin q=q-10; end The iteration should converge logically. However, I am getting an error: "[Synth 8-3380] loop condition does not converge after 2000 iterations" I checked the post - Use of For loop in always block. It says that the number of iterations in a loop must be

问题 In the following code: First, I am loading ROM with data and weight at given address. In the same clock I am doing multiplication of data and weight. Finally, I am extending the number of bits from 16-bit to 23-bit. The code compiles without errors but has warnings. I am unable to solve these warnings. module main_module(extended_out,mux_out,data,weight,clk,en,addr); input clk,en; input [2:0] addr; output [7:0] data,weight; output [15:0] mux_out; output [22:0] extended_out; ram_input a1 (clk,

问题 I am having trouble with combination assignment. I do not understand why I cannot use a always combination structure the set my output variables. When I use assign, I do not get the assignment error. I thought assign and always@(*) both means blocking (combinational assignment) module control_unit(input wire [31:0] instruction ,output wire RegDst ,output wire ALUSrc ,output wire RegWrite ,output wire MemRead ,output wire MemWrite ,output wire MemToReg ,output wire Branch ); wire [5:0] opcode;

问题 I have the following code (a primitive "RS-232 signalling" transmitter)... LIBRARY ieee; USE ieee.std_logic_1164.all; entity SerialTX is port( baud_clk : in std_logic; data : in std_logic_vector(7 downto 0); send : in std_logic; serial_out : out std_logic := '0'; busy : out std_logic := '0' ); end entity; ---------------------------------------- architecture behavioural of SerialTX is constant IDLE_BITS : std_logic_vector(10 downto 0) := "00000000001"; signal shifter : std_logic_vector(10

问题 I've got a two-file VHDL project that I'm having beginner's difficulties with. It takes the system clock and use a 30-bit clock divider (of which I'm only using a small number of non-consecutive bits) to drive a primitive serial port module (outgoing TX only) module to spit out 8 bit characters periodically. It seems that during the synthesis process, many of the essential signals are being removed by the optimizer, which I didn't expect. The top level file "Glue.vhd"... library IEEE; use