Initializing memory in netlist VHDL

问题

After synthesizing a processor code using Synopsis DC tool

Now I want to initialize 2 rams included in 2 components in this design using .mem files

how do I achieve that using the netlist file I have - the output of synthesizing - because I want to test if synthesizing was done right by testing the same code again on processor

It was easier without before synthesizing just by loading .mem files into those rams and then testing it

Any help

回答1:

Don't bother loading .mem files; just initialise the memories directly in VHDL.

The simplest method - if they are ROMs - is to declare them as constant arrays. If this declaration is in a separate package you can easily script its creation from a hex file created by a compiler or assembler.

Here is an example to get you started

package Memories is

type Address is natural range 0 to 2**8 - 1;
type Byte is std_logic_vector(7 downto 0);

type Memory is array(Address) of Byte;

-- Positional association is convenient if you are filling the whole memory
-- constant ROM1 : Memory := (X"00", X"11", X"22", and so on);
-- I'm not going to type out the lot!

-- Named association is better for a simple test program
constant ROM2 : memory := (
   0     => X"C3",
   1     => X"38",
   2     => X"00",
  16#38# => X"C3",
  16#39# => X"00",
  16#3A# => X"00",
  others => X"FF"
);

end Memories;

If they are RAMs, you can call initialise them from the same constant array.

use Memories.all;
constant ROM : Memory := ROM2;
signal   RAM : Memory := ROM2;

These constructs are correctly handled by even the most primitive synthesis tools I have used in the last five years at least, so I would be very surprised if DC can't do the same.

That initial data must be preserved by the synthesis tool and appear in some form in the netlist. If you can understand that form, you can modify the data if necessary, but it is probably easier to update the source and re-synthesise.

来源：https://stackoverflow.com/questions/16607812/initializing-memory-in-netlist-vhdl

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vhdl

synthesis