Loop Convergence - Verilog Synthesis

问题

I am trying to successively subtract a particular number to get the last digit of the number (without division). For example when q=54, we get q=4 after the loop. Same goes for q=205, output is q=5.

  if(q>10)
    while(q>10)
    begin
    q=q-10;
    end

The iteration should converge logically. However, I am getting an error: "[Synth 8-3380] loop condition does not converge after 2000 iterations"

I checked the post - Use of For loop in always block. It says that the number of iterations in a loop must be fixed.

Then I tried to implement this loop with fixed iterations as well like below (just for checking if this atleast synthesizes):

if(q>10)
    while(loopco<9)
    begin
    q=q-10;
    loopco=loopco-1;
    end

But the above does not work too. Getting the same error "[Synth 8-3380] loop condition does not converge after 2000 iterations". Logically, it should be 10 iterations as I had declared the value of loopco=8.

Any suggestions on how to implement the above functionality in verilog will be helpful.

回答1:

That code can not be synthesized. For synthesis the loop has to have a compile time known number of iterations. Thus it has to know how many subtractions to make. In this case it can't.

Never forget that for synthesis you are converting a language to hardware. In this case the tool needs to generate the code for N subtractions but the value of N is not known.

You are already stating that you are trying to avoid division. That suggest to me you know the generic division operator can not be synthesized. Trying to work around that using repeated subtract will not work. You should have been suspicious: If it was the easy it would have been done by now.

You could build it yourself if you know the upper limit of q (which you do from the number of bits):

wire [5:0] q;
reg  [3:0] rem;
always @( * )
   if (q<6'd10)
      rem = q;
   else if (q<6'd20)
      rem = q - 6'd10;
   else if (q<6'd30)
      rem = q - 6'd20;
   etc.
   else
      rem = q - 6'd60;

Just noticed this link which pops up next to your question which shows it has been asked in the past: How to NOT use while() loops in verilog (for synthesis)?

来源：https://stackoverflow.com/questions/48370869/loop-convergence-verilog-synthesis

标签

verilog

synthesis