quartus | 易学教程

Missing EOF at function

阅读更多关于 Missing EOF at function

问题 I have this VHDL code, it should work as a sine generator with lookup table. I keep getting error "Missing EOF at function", or just "syntax error" in modelsim. I have the syntax from some online tutorial, and it seems to be correct. What is wrong? function WAVE(X : integer) -- here is the error marker return integer is variable foo: integer; begin WITH X SELECT foo := 0 WHEN 0, 4 WHEN 1, 7 WHEN 2, 11 WHEN 3, 14 WHEN 4, 18 WHEN 5, 21 WHEN 6, 25 WHEN 7, 28 WHEN 8, 32 WHEN 9, 35 WHEN 10, 38

QuartusII Synthesis: Enumerated type to State signals (encoding)

阅读更多关于 QuartusII Synthesis: Enumerated type to State signals (encoding)

问题 I am designing an FSM in SystemVerilog for synthesis through the QuartusII (14.1) tool to put on an Altera FPGA. I am using an enum declaration to make the code much more reasonable: typedef enum logic [7:0] { CMD_INIT, CMD_WAIT, CMD_DECODE, CMD_ILLEGAL, CMD_CMD0, ... } cmd_st; ... cmd_st cs, ncs; ... Whenever Quartus synthesized this state machine, it seems to create a one-hot encoding despite the logic [7:0] part of the type. As in, when I got to add the states to SignalTap, I get all of

Quartus II -Warning (15714):Some pins have incomplete I/O assignments. Refer to the I/O Assignment

阅读更多关于 Quartus II -Warning (15714):Some pins have incomplete I/O assignments. Refer to the I/O Assignment

Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details 警告（15714）：某些管脚的I/O分配不完整。有关详细信息，请参阅I/O分配警告报告 The incomplete I/O warnings are not listed with the other warnings. You manually need to go into the fitter report and select "I/O Assignment Warnings report". You should then see the list of missing assignments. 需要规定信号强度，In the pin planner in the pin list there's a column called Current Strength. If it doesn't show up there, right-click your mouse in the pin list and select customize columns.... You can add the currenth strenght column

Match Simulation and Post-Synthesis Behavior in VHDL

阅读更多关于 Match Simulation and Post-Synthesis Behavior in VHDL

问题 This question is an extension of the another shown here, VHDL Process Confusion with Sensitivity Lists However, having less than 50 Rep points, I was unable to comment for further explanation. So, I ran into the same problem from the link and accept the answer shown. However, now I am interested in what the recommended approach is in order to match simulation with post-synthesis behavior. The accepted answer in the link states that Level Sensitive Latches are not recommended as a solution due

wait statement must contain condition clause with UNTIL keyword

阅读更多关于 wait statement must contain condition clause with UNTIL keyword

问题 The following VHDL is to be used to test bench. I keep getting an error on the first wait statement during analysis : "wait statement must contain condition clause with UNTIL keyword" I have several working test benches written this way. I can't seem to find what the error might be. `library IEEE; USE IEEE.std_logic_1164.all; entity case_ex_TB is end; architecture simple_test of case_ex_TB is --- DUT Component Declaration --- component case_ex port( clk, rstN: IN std_logic; color: OUT std

Prevent compiler from optimizing logic away

阅读更多关于 Prevent compiler from optimizing logic away

问题 I'd like to generate a reset signal (active high) that will last for a short period of time. I achieved it by following code: always @(posedge clk or negedge rst_n or posedge data) begin if(~rst_n | data) data <= 1'b0; else if(ena) data <= 1'b1; else data <= data; end Which is synthesized to D flip-flop : My generated signal will be 1 only for time equal to propagation time through OR gate. Now I want to remove rst_n signal. But if I do that, I receive the following D flip-flop : In that case

FPGA学习笔记——点亮LED

阅读更多关于 FPGA学习笔记——点亮LED

软件平台：win7（64bit） + Quartus II 9.1 (64-Bit) 硬件平台：东理电子Easy-FPGA Cyclone II EP2C5T114C8N 这个开发板买了很长时间了，买来后一直放那，下面来一个点灯的例子。 1. 实验任务点亮发光二极管。通过这个实验，熟悉并掌握 CPLD/FPGA 开发软件 Quartus II 的使用方法和开发流程以及 Verilog HDL 的编程方法。 2. 实验环境软件实验环境为 Quartus II 9.1 开发软件。 3. 实验原理 FPGA 器件同单片机一样，为用户提供了许多灵活的独立的输入/输出 I/O 口（单元）。 FPGA 每个 I/O 口可以配置为输入、输出、双向、集电极开路和三态门等各种组态。作为输出口时， FPGA 的 I/O 口可以吸收最大为 24mA 的电流，可以直接驱动发光二极管 LED 等器件。图 1. 1 为 8 个发光二极管硬件原理图。通过原理图可知如果要点亮这八个 LED，所以只要正确分配并锁定引脚后，在相应的引脚上输出相应低电平“ 0”，就可实现点亮该发光二极管的功能。图 1. 1 发光二极管 LED 硬件原理图 4. 实验程序 (1) 利用连续赋值 assign 语句来实现（文件名 led_test.v） module led_test (led);

Quartus II use file only in simulation

阅读更多关于 Quartus II use file only in simulation

问题 I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component includes statements which are not syntesizeable). My simulation runs if I remove E from my Testbench, but when I want to include E in my Testbench, I get the error from modelsim: my_testbench.vhd(197): (vcom-1195) cannot find expanded name "mylib.only_for_simulation". How could I make Quartus/Modelsim

Quartus II use file only in simulation

阅读更多关于 Quartus II use file only in simulation

模型机CPU设计——RAM和稳定器（13）

阅读更多关于模型机CPU设计——RAM和稳定器（13）

RAM和稳定器 1 RAM可以根据quartus直接生成LPM_RAM_IO，实现读外接文件mif的读写 RAM接口和功能由quartus提供：但是RAM存在着不稳定的问题，会出现读取操作不是由下降沿控制而只受到控制信号控制的问题，所以这个时候我们用VHDL设计一个稳定器来稳定RAM的读取操作： Stabilizer稳定器设计：（1）部件功能：稳定器用来配合RAM使用，处理因为RAM输出的数据不稳定问题。（2）接口设计：输入： EN：使能信号，1有效 Clk：时钟信号 I[7…0]:数据输入，由RAM提供数据的输入输出： Bus[7…0]数据输出，连接到总线Bus RTL视图（3）功能实现：当EN有效为1时：如果clk=1，那么将输入加载到输出，否则输出保存值如果使能为0：输出高阻态，来隔绝总线，防止总线冲突 VHDL设计：（4）功能仿真验证：仿真结果：时钟为2.5ns: 使能EN=1，clk=1，输入X=00000001，将输入加载到输出，BU=00000001；时钟为3.5ns: 使能EN=1，clk=1，输入X=00000001，将输入加载到输出，BU=00000001；时钟为1.0ns: 使能EN=1，clk=0，输入X=00000001，将寄存器保存的值输出，BU=00000000；时钟为5.0ns: 使能EN=0，clk=0

订阅 quartus