quartus

Compiling *.vhdl into a library, using Altera Quartus II

由 拈花ヽ惹草 提交于 2019-12-18 09:02:08
问题 I am trying to use 'Floating point and Fixed point package' as a part of my filter design in VHDL. I am using Altera Quartus II as the development environment. I downloaded the file package from the website: http://www.vhdl.org/fphdl/, now available at http://web.archive.org/web/20160305202256/http://www.vhdl.org/fphdl/ In their user guide, below is mentioned: 'fixed_float_types_c.vhdl', 'fixed_pkg_c.vhdl' and 'float_pkg_c.vhdl' should be compiled into a library called "ieee_proposed".

Quartus II 13.1添加器件库方法

由 主宰稳场 提交于 2019-12-17 12:36:38
第一次安装Quartus II 选用了13.1版本 1、如何下载器件库 首先打开这个下载地址： http://dl.altera.com/?edition=standard （需注册intel账号） 2、在网页中选择版本号（例如13.1/19.1等版本）和系统（Windows/Linux） 3、下载器件库文件，将下载完成的 .qzd 文件，一定要放到 安装 Quartus II 软件的 bin 目录下（例如本机文件路径D:\altera\13.1\quartus\bin）。 4、安装过程： （1）、首先找到自己的菜单里面的： Quartus II 13.01 Device Installer打开，位置如下图所示： 打开之后，点击Next （2）、会出现如下图所示。将默认的C盘文件位置，设置为Quartus II安装文件 bin 目录下（例如：D:\altera\13.1\quartus\bin本机安装位置） （3）点击Next 进入下一步，并选择你所要安装的器件库文件，浅颜色为已安装成功的文件，深颜色为未安装文件，打勾✔选择后点击Next 进入下一步 （4）点击安装完成后出现窗口的的Finish，器件库的安装完成。 来源： CSDN 作者： 逗比不是我 链接： https://blog.csdn.net/weixin_40663623/article/details

VHDL sequential conditional signal assignment statement error

由 血红的双手。 提交于 2019-12-13 19:42:18
问题 In my VHDL code I have an error in sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in; . I don't think it is a syntax error. But Quartus shows an error at that point. I don`t understand why it's an error. Can anyone provide information: -- Error-- Error (10500): VHDL syntax error at S8BT16B.vhd(35) near text "when"; expecting ";" library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; use ieee.std_logic_arith.all; use work.fft_package.all; entity S8BT16B

Issue with parameters in Modelsim

由 吃可爱长大的小学妹 提交于 2019-12-13 15:41:25
问题 Recently I've came across following issue: in Quartus software I've defined my Verilog module as follows: module module_name( input [w1-1:0] in1, input [w2-1:0] in2, output [w1-1:0] out1 ); parameter w1 = 16; parameter w2 = 8; ... endmodule This module compiled without any issues. But, when I tried to simulate that code in Modelsim(-Altera) 10.3d, I got following errors: (vlog-2730) Undefined variable: 'w1'. (vlog-2388) 'in1' already declared in this scope (module_name) (vlog-2730) Undefined

Integer to unsigned conversion going wrong VHDL quartus

由 我与影子孤独终老i 提交于 2019-12-12 05:38:50
问题 I am having problem with an output error in a waveform, basically my code works as a counter, when i have a load signal equal '1' the counter goes up, if the load signal is '0' the counter doesn't counts. I have a clear signal to get the counter in 0, my problem is in the output, the output shows always the same value and doesn't get in 0 when the clear signal is equal 1. Below the waveform: Below the code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tot is

VHDL program doesn' t compile

由 最后都变了- 提交于 2019-12-12 04:11:13
问题 I am trying to create a VHDL ALU with structural way that does the following operations: 1)ADDITION 2)SUBSTRACTION 3)LOGIC AND 4)LOGIC OR I'm running my code in Quartus II and it finds some errors at compilation. Here is my code : library ieee; use ieee.std_logic_1164.all; use work.basic_func.all; entity askhsh1 is port ( a : in std_logic_vector(15 downto 0); b : in std_logic_vector(15 downto 0); coin : in std_logic; coout : out std_logic; s : in std_logic_vector(15 downto 0); d : in std

Shift Right (srl) going wrong on VHDL Quartus II

由 荒凉一梦 提交于 2019-12-12 03:51:39
问题 I'm trying to make a 8-bit Sequential Multiplier on Quartus II. I did all the simulations of all blocks, but one is showing error on the VWF simulation. The sum_reg block it's doing a infinite shift in a very small time interval. In the "dark blue" part of waveform simulation, on o_DOUT, it's when the shift gones infinite until the MSB goes to the LSB. The image below shows what happens in the dark blue part of the simulation: Someone know what's happen? Below the code: Sum register(where the

Unknown values (X) in simulation of parking lot gate

由 纵饮孤独 提交于 2019-12-12 02:11:44
问题 I am designing a parking-lot gate in VHDL. When I simulate it using Quartus VWF files, I am getting unknown values (X), but I don't know why. Basically you just have to validate your card ( Sin ) and the gate opens for 10 seconds. And when a car exits the parking lot ( Sout ), it counts the total cars at the moment inside of the parking lot. I have created the signal Ncarros (to count number of cars) and s_count for the timer. It all compiles correctly. But when I'm testing it using a VWF

Verilog: on left-hand side of assignment must have a variable data type

由 天涯浪子 提交于 2019-12-11 12:48:59
问题 I am having trouble with combination assignment. I do not understand why I cannot use a always combination structure the set my output variables. When I use assign, I do not get the assignment error. I thought assign and always@(*) both means blocking (combinational assignment) module control_unit(input wire [31:0] instruction ,output wire RegDst ,output wire ALUSrc ,output wire RegWrite ,output wire MemRead ,output wire MemWrite ,output wire MemToReg ,output wire Branch ); wire [5:0] opcode;

What happens when there are multiple architectures on a single entity?

由 江枫思渺然 提交于 2019-12-11 10:42:27
问题 Suppose one has an entity which has two architectures defined. Those two architectures work with the same entity (obviously) and subsequently the two set the output pins to different values. My question is, how does the program (simulator) determine what the output should be (i.e. which architecture to choose)? Here is an example: library ieee; use ieee.std_logic_1164.all; entity Exercise_4 is generic (n : integer := 4); port( a, b : std_logic_vector (n-1 downto 0); clk, rst : std_logic; q,
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