Passing parameters to Verilog modules
问题 I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different methodologies. Which of these methods is the best way to parametrize modules? What is the difference? Is it vendor-dependent (Altera vs Xilinx)? The first method: Module definition: module busSlave #(parameter DATA_WIDTH = 1) ( input [DATA_WIDTH-1:0]