modelsim

问题 I'm attempting to compile in ModelSim 10.0 and I receive a compile error stating: 'Cannot read output status'. Here's a snippet of the code. It'd be brilliant if someone could tell me what I'm doing wrong. entity controller_entity is generic( entryCount : positive := 2; ....); port( clk : in std_logic; .... entry_car_entered : out std_logic_vector(0 to entryCount-1) ); end entity controller_entity; architecture controller_v1 of controller_entity is signal cars_entered : std_logic_vector(0 to

问题 I have a 32 bit barrel shifter using behavior architecture. Now I need to convert it to an n-bit shifter. The problem that I'm facing is that there is some kind of restriction to the for loop that I have to put a constant as sentinel value. Following is my Code library IEEE; use IEEE.std_logic_1164.all; Entity bshift is -- barrel shifter port (left : in std_logic; -- '1' for left, '0' for right logical : in std_logic; -- '1' for logical, '0' for arithmetic shift : in std_logic_vector(4 downto

问题 My testbench uses a function that is defined in a modelsim package (init_signal_spy). So I can't use this testbench with a different simulator than ModelSims vsim, for example Candence's ncsim. But there is an equivalent function for ncsim (nc_mirror) in the cadence packages. The solution is that I need to have two different testbenches. But I want to use only one. One solution could be, to define a package only if some constant is set. But I don't know if that is possible. 回答1: The general

问题 Recently I've came across following issue: in Quartus software I've defined my Verilog module as follows: module module_name( input [w1-1:0] in1, input [w2-1:0] in2, output [w1-1:0] out1 ); parameter w1 = 16; parameter w2 = 8; ... endmodule This module compiled without any issues. But, when I tried to simulate that code in Modelsim(-Altera) 10.3d, I got following errors: (vlog-2730) Undefined variable: 'w1'. (vlog-2388) 'in1' already declared in this scope (module_name) (vlog-2730) Undefined

问题 I want to use four push buttons as inputs and three seven-segment LED displays as outputs. Two push buttons should step up and down through the sixteen RAM locations; the other two should increment and decrement the contents of the currently-displayed memory location. I am now trying to simulate my design using ModelSim test benches, with button presses. Here is what I believe to be the relevant portions of my code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity

问题 I have a record in VHDL that contains a pointer ( access ). I need to create a function that receives this record as parameter and from its data write in a file. But simulating with MODELSIM I get the following error: **Error: (vcom-1462) Illegal declaration of constant "xxx" of type x_file_format (type is or contains access type). How can I pass a pointer as parameter to a function? 回答1: Function parameters can only be constant (or signal or file) inputs. Access types must be variables.

问题 I designed a primality testing for Rabin Miller algorithm in behavioral type. I used functions to create my modules. Unfortunately, when I tried to synthesize it by my Altera Kit via Quartus, I realized that function are not synthesize. Here I will write my whole program, and I really need you help to give me at least some hints to change it to structural as it is my senior design project. Here is my program: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity

问题 I'm trying to simulate ICE5LP1K FPGA internal oscillator on ModelSim. My design includes the following instance: SB_HFOSC OSCInst1 ( .CLKHFEN(1'b1), .CLKHFPU(1'b1), .CLKHF(CLKLF) ) I included sb_ice_syn.v file but have a design loading error: Error: ../testbench/sb_ice_syn.v(26066): Module 'SB_HFOSC_CORE' is not defined I'm not able to find SB_HFOSC_CORE module in the lattice installation folder. Where can I find the missed modules? 回答1: Doing ModelSim simulation of a Lattice ICE40 family

问题 Suppose one has an entity which has two architectures defined. Those two architectures work with the same entity (obviously) and subsequently the two set the output pins to different values. My question is, how does the program (simulator) determine what the output should be (i.e. which architecture to choose)? Here is an example: library ieee; use ieee.std_logic_1164.all; entity Exercise_4 is generic (n : integer := 4); port( a, b : std_logic_vector (n-1 downto 0); clk, rst : std_logic; q,

问题 I am trying to simulate my VHDL file, but am running into the following error: # ** Error: (vcom-11) Could not find work.lab1. # # ** Error: (vcom-1195) Cannot find expanded name "work.lab1". # # ** Error: Unknown expanded name. # ** Error: VHDL Compiler exiting # ** Error: c:/altera/12.1/modelsim_ase/win32aloem/vcom failed. # Error in macro ./DE2_TOP_run_msim_rtl_vhdl.do line 8 # c:/altera/12.1/modelsim_ase/win32aloem/vcom failed. # while executing # "vcom -93 -work work" I compiled the code