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Why can't I call a function in a constant declaration, that is defined in the same package in ModelSim?

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问题 I have a VHDL package that defines a function (forward declaration) and a constant. The constant's value is calculated by that function, whose body is located in the package body. As of now ModelSim/QuestaSim is the only tool that does not like this code. It needs 2 packages so the body was parsed before the constant declaration. package test is function mytest(param : boolean ) return boolean; constant value : boolean := mytest(TRUE); end package; package body test is function mytest(param :

How does signal assignment work in a process?

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问题 I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this example here: ... signal x,y,z : bit; ... process (y) begin x<=y; z<=not x; end process; The example says this: If the signal y changes then an event will be scheduled on x to make it the same as y. Also, an event is scheduled on z to make it the opposite of x. The question is, will the value of z be the opposite of y? Of course, the answer is no, because when the second

Creating a Register File with a Test Bench

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问题 So I would like to simulate a simple register file and test it. But it's been pretty confusing. I put together what I hope is a functional register file based on the notes that my professor provided, but now I'm struggling to create the test bench for it. I guess the main thing is how it has two DATA's and ADDR's (he showed an example of a memory file which only has one of each). Anyway, for my test bench I simply want to write some numbers to the register like in a for loop and instantiate

Accumulator in VHDL

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问题 this my code for an accumulator: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity akkumulator is generic (N : natural:=1); port(rst: in bit; clk: in bit; B : in natural range 0 to N-1; A : out natural range 0 to N-1); end akkumulator; architecture verhalten of akkumulator is begin p1: process(rst, clk) variable ergebnis : natural range 0 to N-1; begin if (rst = '1') then ergebnis := 0; elseif (clk'event and clk = '1') then ergebnis := ergebnis + B; end if; A <=

Can't compile VHDL package - Modelsim error: (vcom-1576) expecting END

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问题 Quite a simple one, but I am pulling my hair out and need some fresh eyes. The problem is detailed below, originally I had the issue with a much larger package containing multiple items so stripped everything back to basics and still can't work it out... thanks in advance g Simple code: ---------------------------------- -- LIBRARY_DECLARATIONS ---------------------------------- library STD; use STD.standard.all; ---------------------------------- library IEEE; use IEEE.std_logic_1164.all; --

Quartus II use file only in simulation

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问题 I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component includes statements which are not syntesizeable). My simulation runs if I remove E from my Testbench, but when I want to include E in my Testbench, I get the error from modelsim: my_testbench.vhd(197): (vcom-1195) cannot find expanded name "mylib.only_for_simulation". How could I make Quartus/Modelsim

Quartus II use file only in simulation

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基于FPGA的图像处理（一）--System Generator介绍

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计算机视觉系统通常需要进行大量的信息处理才能够得到所需要的信息。目前主要有CPU、GPU、ASIC、DSP、FPGA等计算平台。常用的计算机视觉系统通过通用计算机进行视觉信息处理，但是，由于CPU的计算能力有限，对于一些计算复杂度很高的视觉算法，其处理速度常常难以满足系统的实时性需要。 GPU具有高度的并行计算能力，可以较好地解决计算速度的问题，然而，基于GPU的计算机视觉系统存在着功耗较高、体积较大的缺点，难以满足依靠自身所带电池供电并长时间工作的服务机器人等应用系统的需要。利用专用集成电路ASIC实现视觉处理算法，可以解决视觉系统性能和体积、功耗之间的矛盾，是高性能嵌入式视觉系统的一种有效的解决方案。然而，ASIC开发周期长、修改不方便，通用性较差。 FPGA可以通过编程方便地修改其内部的逻辑功能，从而实现高速的硬件计算和并行运算，是高性能嵌入式视觉系统的一种更加方便的解决方案。基于FPGA的嵌入式视觉系统的功耗远远低于基于CPU和GPU的视觉系统，FPGA的功耗通常不到1W，而高性能CPU和GPU的功耗通常都在100W以上。随着技术的不断进步，FPGA的集成度越来越高，可以实现的设计规模越来越大，而功耗则越来越低。因此，基于FPGA的嵌入式视觉系统将是计算机视觉系统的重要发展方向。使用FPGA进行图像处理时，既要对赢家有很深的了解，同时又需要对图像处理的算法很熟悉

Where can I find a definitive list of the ModelSim error codes?

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问题 I am running some VHDL through ModelSim. Each error and warning has its own error code (like this: (vcom-1292) Slice range direction "downto" specified in slice with prefix of unknown direction. This is just an example message; I understand what it means. I assume that Mentor has a list of all possible error codes and a more elaborate description of what they mean, and how to avoid them. I did not find this error code in the PDFs that come with ModelSim, nor did I find it through Google. Any

Debugging Iteration Limit error in VHDL Modelsim

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问题 I'm writing VHDL code for a d-flip-flop on Modelsim and I get an error when I try to simulate it: Error: (vsim-3601) Iteration limit reached at time 400 ps. I'm not sure what it means, but I've looked through much of my source code for errors to no success. Can anyone guess what the problem might be? 回答1: This error usually indicates that ModelSim is stuck in an infinite loop. In VHDL, this can happen when a signal is placed in the sensitivity list and this signal is changed in the process.